Flags, no-operation and power
| Instruction | Encoding | Chip | What it does |
|---|---|---|---|
nop | 0000 0000 0000 1001 | SH-1 | Does nothing. The usual delay-slot filler. |
clrt | 0000 0000 0000 1000 | SH-1 | T = 0. |
sett | 0000 0000 0001 1000 | SH-1 | T = 1. |
clrmac | 0000 0000 0010 1000 | SH-1 | MACH = MACL = 0. |
clrs | 0000 0000 0100 1000 | SH-3 | S = 0 (no saturation in mac.w and mac.l). |
sets | 0000 0000 0101 1000 | SH-3 | S = 1. |
sleep | 0000 0000 0001 1011 | SH-1 | Stop the processor until an interrupt or a reset (the standby modes depend on the chip's registers). Privileged on SH-3 and later. |
ldtlb | 0000 0000 0011 1000 | SH-3 | Load the TLB entry chosen by MMUCR from PTEH, PTEL (and PTEA). Privileged. |
brk | 0000 0000 0011 1011 | SH-4A | Break: raises a user-break exception for a debugger. The chip that introduced it is from memory. |
Control registers: LDC and STC
The ldc and stc instructions move the control registers SR, GBR and VBR (SH-1), SSR, SPC and the other-bank registers (SH-3), SGR and DBR (SH-4). The
.l forms use memory with post-increment (ldc.l @Rm+,Reg) or pre-decrement (stc.l Reg,@-Rn), which is how an interrupt handler saves and restores registers on the stack.
In SH-3 and later every one of them except GBR is privileged.
| Instruction | Encoding | Chip | What it does |
|---|---|---|---|
ldc Rm,SRldc Rm,GBRldc Rm,VBRldc Rm,SSRldc Rm,SPCldc Rm,DBRldc Rm,Rb_BANK |
0100 mmmm 0000 11100100 mmmm 0001 11100100 mmmm 0010 11100100 mmmm 0011 11100100 mmmm 0100 11100100 mmmm 1111 10100100 mmmm 1bbb 1110 |
SH-1 SH-1 SH-1 SH-3 SH-3 SH-4 SH-3 | Load the control register from Rm. Rb_BANK is r0_bank to r7_bank: the register of the bank that is not selected by SR.RB. |
ldc.l @Rm+,SRldc.l @Rm+,GBRldc.l @Rm+,VBRldc.l @Rm+,SSRldc.l @Rm+,SPCldc.l @Rm+,DBRldc.l @Rm+,Rb_BANK |
0100 mmmm 0000 01110100 mmmm 0001 01110100 mmmm 0010 01110100 mmmm 0011 01110100 mmmm 0100 01110100 mmmm 1111 01100100 mmmm 1bbb 0111 |
SH-1 SH-1 SH-1 SH-3 SH-3 SH-4 SH-3 | Load the control register from the longword at Rm, then add 4 to Rm. |
stc SR,Rnstc GBR,Rnstc VBR,Rnstc SSR,Rnstc SPC,Rnstc SGR,Rnstc DBR,Rnstc Rb_BANK,Rn |
0000 nnnn 0000 00100000 nnnn 0001 00100000 nnnn 0010 00100000 nnnn 0011 00100000 nnnn 0100 00100000 nnnn 0011 10100000 nnnn 1111 10100000 nnnn 1bbb 0010 |
SH-1 SH-1 SH-1 SH-3 SH-3 SH-4 SH-4 SH-3 | Store the control register in Rn. |
stc.l SR,@-Rnstc.l GBR,@-Rnstc.l VBR,@-Rnstc.l SSR,@-Rnstc.l SPC,@-Rnstc.l SGR,@-Rnstc.l DBR,@-Rnstc.l Rb_BANK,@-Rn |
0100 nnnn 0000 00110100 nnnn 0001 00110100 nnnn 0010 00110100 nnnn 0011 00110100 nnnn 0100 00110100 nnnn 0011 00100100 nnnn 1111 00100100 nnnn 1bbb 0011 |
SH-1 SH-1 SH-1 SH-3 SH-3 SH-4 SH-4 SH-3 | Subtract 4 from Rn, then store the control register there. |
System registers: LDS and STS
The lds and sts instructions move MACH, MACL, PR and, on the SH-4, FPUL and FPSCR. They are not privileged.
Loading FPSCR changes the SZ, PR and FR modes that decide how the floating-point instructions that follow read.
| Instruction | Encoding | Chip | What it does |
|---|---|---|---|
lds Rm,MACHlds Rm,MACLlds Rm,PRlds Rm,FPULlds Rm,FPSCR |
0100 mmmm 0000 10100100 mmmm 0001 10100100 mmmm 0010 10100100 mmmm 0101 10100100 mmmm 0110 1010 |
SH-1 SH-1 SH-1 SH-4 SH-4 | Load the system register from Rm. |
lds.l @Rm+,MACHlds.l @Rm+,MACLlds.l @Rm+,PRlds.l @Rm+,FPULlds.l @Rm+,FPSCR |
0100 mmmm 0000 01100100 mmmm 0001 01100100 mmmm 0010 01100100 mmmm 0101 01100100 mmmm 0110 0110 |
SH-1 SH-1 SH-1 SH-4 SH-4 | Load the system register from the longword at Rm, then add 4 to Rm. lds.l @r15+,pr is the usual function epilogue. |
sts MACH,Rnsts MACL,Rnsts PR,Rnsts FPUL,Rnsts FPSCR,Rn |
0000 nnnn 0000 10100000 nnnn 0001 10100000 nnnn 0010 10100000 nnnn 0101 10100000 nnnn 0110 1010 |
SH-1 SH-1 SH-1 SH-4 SH-4 | Store the system register in Rn. sts macl,Rn reads a multiplication result. |
sts.l MACH,@-Rnsts.l MACL,@-Rnsts.l PR,@-Rnsts.l FPUL,@-Rnsts.l FPSCR,@-Rn |
0100 nnnn 0000 00100100 nnnn 0001 00100100 nnnn 0010 00100100 nnnn 0101 00100100 nnnn 0110 0010 |
SH-1 SH-1 SH-1 SH-4 SH-4 | Subtract 4 from Rn, then store the system register there. sts.l pr,@-r15 is the usual function prologue. |
Privileged instructions
On SH-3 and later the processor is in user mode or privileged mode (SR.MD). In user mode the following raise a general illegal instruction exception:
ldc and stc (and their .l forms) of every register except GBR, rte, sleep, ldtlb. The SH-1 and SH-2 have no modes. The explorer notes "privileged" on these.
The list is from the manuals as remembered; the instruction-cache and operand-cache instructions have their own rules on the cache page.
Not described
Known, not yet covered
- Reference and viewer: SH-2A control instructions (
ldc Rm,TBR,stc TBR,Rn,resbank,ldbank,stbank) and the DSP control registers.
Unknown
- Reference: the exact privilege of each register move and whether SH-4A's SGR and DBR moves differ.