SuperH Registers and Status Bits

General registers

Sixteen 32-bit registers, r0 to r15. They are all alike except where an instruction names one:

r0 is the index register of the @(r0,Rn) addressing mode and the only register the byte and word @(disp,Rn) and @(disp,GBR) moves, the immediate logic instructions (and #imm,r0 and the others), cmp/eq #imm,r0 and mova can use.
r15 is the stack pointer by convention (the hardware does not make it special, except that an exception on SH-1 and SH-2 pushes there). The disassembly can write it sp.
The calling convention of the GNU compiler passes the first four arguments in r4 to r7, returns in r0, keeps r8 to r14 across calls, and uses r14 as the frame pointer; this is a convention of compilers, not of the chip.

Register banks (SH-3, SH-4 and later). There are two sets of r0 to r7. With the SR bit RB = 0 the code sees bank 0, with RB = 1 bank 1; an exception sets RB = 1 so its handler has eight free registers. ldc Rm,Rn_BANK and stc Rm_BANK,Rn reach the other bank's r0_bank to r7_bank. r8 to r15 are not banked.

Control and system registers

Register	Chips	What it is
`PC`	all	The program counter. A PC-relative operand counts from the address of the instruction plus 4; `mov.l` and `mova` clear the low two bits of that sum first.
`PR`	all	The procedure register: `bsr`, `bsrf` and `jsr` put the return address (the address after the delay slot) here; `rts` jumps to it.
`GBR`	all	Global base register for `@(disp,GBR)` and `@(r0,GBR)`, the byte logic instructions and TST.B.
`VBR`	all	The base of the exception vector table (SH-1, SH-2) or of the exception handlers (SH-3 and later).
`MACH`, `MACL`	all	The multiply-accumulate registers: the 64-bit result of `dmuls.l`, `dmulu.l`, `mac.l`; the 32-bit result of `mul.l`, `muls.w` and `mulu.w` goes in `MACL`.
`SR`	all	The status register, below.
`SSR`, `SPC`	SH-3 and later	The saved status register and saved program counter: an exception copies SR and the address to return to here, and `rte` restores them.
`SGR`	SH-4 and later	The saved general register 15: the stack pointer at the time of an exception. Read-only: `stc SGR,Rn`.
`DBR`	SH-4 and later	The debug base register: the base of the user-break handler.

The status register

Bit	Name	Chips	Meaning
0	`T`	all	The true bit: set by compares, `tst`, shifts and carries; tested by `bt` and `bf`; read with `movt`.
1	`S`	all	Saturation for `mac.w` and `mac.l` (`sets` and `clrs`, SH-3 and later, set and clear it).
4 to 7	`I3 to I0`	all	The interrupt mask level: an interrupt of a priority not above this is held off.
8, 9	`Q`, `M`	all	The two bits of `div0s`, `div0u` and `div1` (the division step).
15	`FD`	SH-4 and later	FPU disable: with FD = 1 any floating-point instruction raises an FPU disable exception.
28	`BL`	SH-3 and later	Block: exceptions and interrupts are held off.
29	`RB`	SH-3 and later	Which register bank is r0 to r7 (see above).
30	`MD`	SH-3 and later	Privileged mode (1) or user mode (0). In user mode the instructions marked privileged raise an illegal instruction exception.

Floating-point registers (SH-4 and later)

The FPU has two banks of sixteen 32-bit registers. FPSCR.FR says which one is the front bank, named fr0 to fr15; the other is the back bank, named xf0 to xf15. frchg swaps them. The same registers have wider names: dr0, dr2 ... dr14 are pairs of front registers (double precision), xd0 ... xd14 the pairs of back registers, fv0, fv4, fv8, fv12 the four-element vectors of the front bank, and xmtrx the 4 x 4 matrix in the back bank. FPUL is the 32-bit communication register between the integer and the floating-point side (lds, sts, flds, fsts, float, ftrc move through it).

FPSCR bit	Name	Meaning
0 to 1	`RM`	Rounding mode: 0 nearest, 1 toward zero.
2 to 6	flags	The sticky exception flags (inexact, underflow, overflow, divide by zero, invalid).
7 to 11	enable	Which exceptions trap.
12 to 17	cause	The exceptions of the last instruction (including FPU error).
18	`DN`	Denormalisation mode: flush denormals to zero.
19	`PR`	Precision: 0 single, 1 double. Changes what the arithmetic instructions are.
20	`SZ`	Transfer size: 0 moves 32 bits, 1 moves 64 bits. `fschg` toggles it.
21	`FR`	Which bank is the front bank. `frchg` toggles it.

Not described

Known, not yet covered

Reference: the on-chip peripheral registers, the MMU registers (PTEH, PTEL, TTB, TEA, MMUCR), the cache registers and the exception registers (EXPEVT, INTEVT, TRA), which are memory-mapped, not instruction operands.
Reference: the SH-2A, SH-DSP and SH-3E registers (TBR, the DSP registers, the SH-2A banked set).

Unknown

Reference: the register facts are from the Renesas software manuals as remembered; none was open while writing this page.