Instructions
"Delay slot: yes" means the next instruction runs before the branch takes effect (see Delay slots).
A branch cannot itself be in a delay slot. The target of a PC-relative branch is PC + 4 + displacement * 2.
| Instruction | Encoding | Chip | Delay slot | What it does |
|---|---|---|---|---|
bt label | 1000 1001 dddddddd | SH-1 | no | Branch when T = 1. The displacement is signed 8 bits times 2: -256 to +254 bytes from PC + 4. |
bf label | 1000 1011 dddddddd | SH-1 | no | Branch when T = 0. The same range. |
bt/s label | 1000 1101 dddddddd | SH-2 | yes | Branch when T = 1, with a delay slot that runs whether or not the branch is taken. |
bf/s label | 1000 1111 dddddddd | SH-2 | yes | Branch when T = 0, with a delay slot. |
bra label | 1010 dddddddddddd | SH-1 | yes | Branch always. The displacement is signed 12 bits times 2: -4096 to +4094 bytes. |
bsr label | 1011 dddddddddddd | SH-1 | yes | Call: PR = the address of the instruction plus 4, then branch as bra. |
braf Rm | 0000 mmmm 0010 0011 | SH-2 | yes | Branch to PC + 4 + Rm: a position-independent jump table. |
bsrf Rm | 0000 mmmm 0000 0011 | SH-2 | yes | Call to PC + 4 + Rm; PR = the return address. |
jmp @Rm | 0100 mmmm 0010 1011 | SH-1 | yes | Jump to the address in Rm. |
jsr @Rm | 0100 mmmm 0000 1011 | SH-1 | yes | Call the address in Rm; PR = the instruction address plus 4. Calls beyond the bsr range load the address with mov.l @(disp,PC),Rm first. |
rts | 0000 0000 0000 1011 | SH-1 | yes | Return: jump to PR. |
rte | 0000 0000 0010 1011 | SH-1 | yes | Return from an exception. SH-1 and SH-2: PC and SR are popped from the stack. SH-3 and later: PC = SPC and SR = SSR (privileged). |
trapa #imm | 1100 0011 iiiiiiii | SH-1 | no | Software trap: an exception with the 8-bit immediate as the vector number (SH-1, SH-2) or stored in TRA (SH-3 and later). Used for system calls. |
How code uses them
- A function call:
mov.l @(disp,PC),r1(the address of the callee from a literal),jsr @r1, and in the delay slot the last argument load. - A return:
rtsand, in its slot, the last instruction of the epilogue (mov.l @r15+,r14). - A loop:
dt r3thenbf/sback, with the next instruction of the loop body in the slot. - A switch: a jump table of 16-bit offsets,
braf.
Not described
Known, not yet covered
- Reference and viewer: the SH-2A
jsr/n,rts/n,rtv/n(no delay slot) and the SH-DSP repeat-loop instructions (setrc,ldrs,ldre).
Unknown
- Reference: where TRAPA's immediate goes on SH-3 and later (TRA) is from memory.