Length and alignment
Every SH-1 to SH-4A instruction is exactly 2 bytes, and must sit at an even address. There is no way to start an instruction in the middle of another, so a decoder that reads a 2-byte aligned address sees exactly what the processor sees; the explorer decodes every 2-byte aligned address of a region (and shows an odd leading byte as a byte only). The SH-2A adds 32-bit instructions, which this decoder does not read yet (see Not described).
The word is fetched in the byte order of the system: big-endian on the Saturn and the 32X (the first byte holds bits 15 to 8), little-endian on the Dreamcast (the first byte holds bits 7 to 0). The chips can run either way; the explorer takes the order from an ELF file, and otherwise from the option. The bit patterns on these pages are always of the 16-bit word as a number.
The fields
The manuals write an encoding as 16 characters, most significant bit first. A 0 or 1 is a fixed bit; the letters are fields:
| Letters | Bits | Meaning |
|---|---|---|
nnnn | 4 (bits 11 to 8) | The destination register, or the register that is both source and destination: Rn. In the floating-point line, the destination FRn, DRn or FVn. |
mmmm | 4 (bits 7 to 4) | The source register Rm. (For the instructions with one operand, such as jmp @Rm and lds Rm,PR, the register is in bits 11 to 8 and the manual writes it mmmm there.) |
iiiiiiii | 8 | An immediate: sign-extended for mov #imm,Rn, add #imm,Rn and cmp/eq #imm,R0; zero-extended for the logic and trap instructions. |
dddd | 4 | A displacement for @(disp,Rn), scaled by the size of the access: x1 (byte), x2 (word), x4 (longword). |
dddddddd | 8 | A displacement for @(disp,GBR) and @(disp,PC) (scaled by the access size), or a signed branch displacement of bt, bf, bt/s, bf/s (x2). |
dddddddddddd | 12 | The signed branch displacement of bra and bsr (x2). |
bbb | 3 (bits 6 to 4) | The number of the other-bank register in ldc Rm,Rn_BANK and stc Rm_BANK,Rn, with bit 7 = 1. |
The top four bits (the first hex digit) group the instructions: 0 stores, multiplies, system and cache; 1 mov.l Rm,@(disp,Rn); 2 stores, logic and multiplies; 3 compares, add and subtract;
4 shifts, control register moves; 5 mov.l @(disp,Rm),Rn; 6 loads, unary operations; 7 add #imm,Rn; 8 byte and word moves with displacement, compare and conditional branches;
9 mov.w @(disp,PC),Rn; A bra; B bsr; C GBR moves, immediate logic, trapa, mova; D mov.l @(disp,PC),Rn; E mov #imm,Rn; F floating point.
PC-relative addresses
PC is the address of the instruction; the hardware uses PC + 4 (two words ahead). So:
bra,bsr,bt,bf,bt/s,bf/s: target =PC + 4 + disp * 2, with disp signed.mov.w @(disp,PC),Rn: the word atPC + 4 + disp * 2.mov.l @(disp,PC),Rnandmova: the longword (or the address) at((PC + 4) with the low two bits cleared) + disp * 4. The displacement is unsigned, so a literal can only be after the instruction; that is why compilers put literal pools after a function.braf Rmandbsrf Rm:PC + 4 + Rm.
The disassembly shows the literal's address next to every PC-relative load. These rules, for an instruction in a delay slot, are explained on the delay slots page.
Not described
Known, not yet covered
- Reference and viewer: the 32-bit SH-2A formats (
movi20,mov.l @(disp12,Rm),Rnand the bit-manipulation instructions) and the parallel DSP formats.
Unknown
- Reference: field layouts were written from the manuals as remembered, then compared with a second hand-written table and with the debugger's SH-4 disassembler (see the overview).