Delayed and non-delayed branches
On SuperH the instruction after a delayed branch, its delay slot, is executed before the branch takes effect. In
jsr @r1 followed by mov #4,r4, the mov runs first, so the callee sees r4 = 4, and the call returns to the
instruction after the delay slot: PR is set to the address of the branch plus 4. The branch target is counted from the branch
itself (PC + 4), not from the slot.
The delayed instructions are bra, bsr, braf, bsrf, jmp, jsr, rts, rte, and (SH-2 and later) the delayed
conditional branches bt/s and bf/s. bt and bf are the non-delayed forms: they have no delay slot. The delay slot of
bt/s and bf/s is executed whether or not the branch is taken, unlike a MIPS branch likely. trapa and the exceptions have no delay slot.
The explorer marks the instruction in a delay slot ("delay slot") so that code reads in the order the processor runs it, and writes "The next instruction is the delay slot" in the note of the branch.
What may not be in a delay slot
Some instructions in a delay slot raise a slot illegal instruction exception. The manuals' list, as remembered, is: every branch, jump and
return (bt, bf, bt/s, bf/s, bra, bsr, braf, bsrf, jmp, jsr, rts, rte), trapa, and the
PC-relative loads (mov.w @(disp,PC),Rn, mov.l @(disp,PC),Rn, mova), because the PC they would use is not the one the
assembler assumed. The explorer shows such an instruction in a slot with the status illegal. Which other instructions are
slot-illegal on SH-3 and later (the manuals mention instructions that rewrite SR) was not confirmed here and is not marked.
A word that is not an instruction at all, in a delay slot, is an ordinary illegal instruction.
Things to know when reading
- The usual compiler idiom is to fill the slot with a useful instruction (
rtsthen the lastmov.l @r15+,r14), or withnop. - A branch whose slot is another delayed branch is a program error; the disassembly shows both and marks the second illegal.
- The explorer decodes every 2-byte aligned address on its own: whether a given word is "in a slot" depends on the word just before it being a delayed branch.
Not described
Known, not yet covered
- Reference: the SH-2A has instructions without delay slot (
jsr/n,rts/n,rtv/n); not decoded.
Unknown
- Reference: the exact list of slot-illegal instructions per chip (see above).