SuperH Floating-Point Instructions (SH-4)

FPSCR modes: one word, several meanings

The floating-point instructions all live in line F (1111 ...). Two bits of the FPSCR register, which the instruction stream does not carry, change what some of them are:

The same bit patterns therefore decode differently: 0xF20C is fmov fr0,fr2 with SZ = 0, and fmov dr0,dr2 with SZ = 1; 0xF200 is fadd fr0,fr2 with PR = 0 and fadd dr0,dr2 with PR = 1. A few instructions exist in only one precision: fmac, fldi0, fldi1, fipr, ftrv, fsca and fsrra need PR = 0; fcnvsd and fcnvds need PR = 1. Used in the wrong mode the manual says the result is undefined and the explorer gives the status unpredictable.

What the explorer tracks. Nothing: it cannot see the value in FPSCR. SZ and PR are options (the options bar of the viewer: "FPSCR.SZ" and "FPSCR.PR") with the default 0, and the choice applies to the whole region. The instructions that change the bits say so in their notes: fschg (toggles SZ), frchg (toggles FR), fpchg (toggles PR, SH-4A), and lds Rm,fpscr and lds.l @Rm+,fpscr (load all bits). Dreamcast code uses fschg in pairs around 64-bit block copies, and lds of a constant from a literal pool at the start of a function to set PR and SZ.

The FR bit swaps which bank is called fr and which xf; it does not change any encoding, so the disassembly does not depend on it.

Arithmetic and comparison

Shown for PR = 0 (single precision, registers FRm, FRn); with PR = 1 the same encodings use DRm, DRn (bits 7 and 11 must be 0). All of these read FPSCR.

Moves, constants, conversion

Vector and matrix instructions

These work on four single-precision values at once: fv0, fv4, fv8, fv12 are the four-element vectors of the front bank, and xmtrx is the 4 x 4 matrix in the back bank (xf0 to xf15). A 3D transform is one ftrv per vertex; a dot product is one fipr. They need PR = 0.

Mode instructions

Not described

Known, not yet covered

• Reference and viewer: the single-precision subsets of the SH-2E and SH-3E, and the SH-2A double-precision unit with its own encodings.
• Viewer: tracking of FPSCR through a function (the viewer takes SZ and PR as options).
• Reference: the exception behaviour (cause and enable bits, denormal handling, the FPU error) and the exact results of fsca, fsrra and fipr, which are not IEEE-exact.

Unknown

• Reference: whether every odd-field encoding with PR = 1 is "reserved" or "undefined" differs between manuals; the explorer says reserved.
• Reference: the encodings were written from memory of the SH-4 manual. The whole line was compared with a second hand-written table (the same author) for all four modes, and the integer part and a part of the FPU (single-precision, SZ = 0) with the debugger's SH-4 disassembler; the double-precision and SZ = 1 forms, FIPR, FTRV, FSCA and FSRRA have no independent check.