SuperH Cache Instructions

Instructions

The SH-3 has one cache instruction; the SH-4 adds the operand-cache block instructions; the SH-4A adds the instruction-cache ones. A cache line is 32 bytes on the SH-4. All take an address in a register, @Rn, and none changes a general register or the T bit. They do not raise an exception for an address that is not cached.

Instruction	Encoding	Chip	What it does
`pref @Rn`	`0000 nnnn 1000 0011`	SH-3	Prefetch the 32-byte line at the address into the operand cache. On the SH-4, an address in 0xE0000000 to 0xE3FFFFFF is a store queue address: `pref` sends the 32 bytes written there to external memory. The Dreamcast uses this for fast block writes to video memory.
`ocbi @Rn`	`0000 nnnn 1001 0011`	SH-4	Operand cache block invalidate: discard the line containing the address, without writing it back.
`ocbp @Rn`	`0000 nnnn 1010 0011`	SH-4	Operand cache block purge: write the line back if it is dirty, then invalidate it.
`ocbwb @Rn`	`0000 nnnn 1011 0011`	SH-4	Operand cache block write back: write the line back if dirty, and keep it.
`movca.l R0,@Rn`	`0000 nnnn 1100 0011`	SH-4	Store R0 at the address; if the line is not in the cache, allocate it without fetching it from memory first (useful when the whole line is about to be written).
`prefi @Rn`	`0000 nnnn 1101 0011`	SH-4A	Prefetch an instruction-cache line.
`icbi @Rn`	`0000 nnnn 1110 0011`	SH-4A	Instruction cache block invalidate: discard the line.
`synco`	`0000 0000 1010 1011`	SH-4A	Synchronise: wait until every earlier load, store, cache operation and prefetch has completed before the next instruction starts.

The two atomic access instructions, movli.l and movco.l, are on the data transfer page.

Not described

Known, not yet covered

Reference: the cache and store-queue control registers (CCR, QACR0, QACR1) and the address-array and data-array access windows.

Unknown

Reference: whether the SH-3 pref and the SH-4 one differ in the store-queue behaviour for every address, and the line size of each chip, are from memory.