Registers
| Register | Size | Use |
|---|---|---|
D0 to D7 | 32 | Data registers. A byte or word operation changes only the low byte or word; the rest is kept. Bit-field offsets, shift counts and bit numbers can come from one. |
A0 to A6 | 32 | Address registers: pointers and index bases. A word operation on one is sign-extended to 32 bits and no condition code changes (MOVEA, ADDA, SUBA, CMPA). |
A7 (SP) | 32 | The stack pointer: USP in user mode, SSP (and on the 68020 to 68040 the master or interrupt stack, MSP and ISP) in supervisor mode. -(A7) pushes, (A7)+ pops. A byte push or pop moves it by 2 to keep it even. |
PC | 32 (24 on the 68000 and 68010) | Program counter. A relative branch is measured from the address of its first extension word, i.e. the instruction address plus 2. |
SR | 16 | Status register: the user byte is the CCR, the system byte holds trace, supervisor, master and interrupt-mask bits. |
FP0 to FP7, FPCR, FPSR, FPIAR | 80, 32, 32, 32 | The floating-point registers of a 68881, 68882, 68040 or 68060; see Floating point. |
Status register and condition codes
| Bit | Name | Meaning |
|---|---|---|
| 15 | T1 (T) | Trace: an exception after every instruction. The 68020 and later have T1 (every instruction) and T0 (bit 14: only changes of flow). |
| 13 | S | Supervisor mode. Privileged instructions (RESET, STOP, RTE, MOVE to SR, MOVE USP, MOVEC, MOVES, the ORI, ANDI and EORI to SR forms, and MOVE from SR on the 68010 and later) cause a privilege violation in user mode. |
| 12 | M | Master/interrupt state (68020 to 68040): selects MSP instead of ISP in supervisor mode. |
| 10–8 | I2 I1 I0 | Interrupt mask: an interrupt of a level not above this is ignored; level 7 cannot be masked. |
| 4 | X | Extend: the carry of multi-word arithmetic and rotates through X. Set by the same operations as C, but not by moves, compares or logical operations. |
| 3 | N | Negative: the top bit of the result. |
| 2 | Z | Zero. After ADDX, SUBX, NEGX and the BCD instructions it is cleared by a non-zero result but never set, so a chain of them gives the zero test of the whole number. |
| 1 | V | Overflow: a signed result that does not fit. |
| 0 | C | Carry or borrow. |
The sixteen conditions of Bcc, DBcc, Scc and TRAPcc:
| Code | Name | True when | Code | Name | True when |
|---|---|---|---|---|---|
| 0 | T | always | 8 | VC | V = 0 |
| 1 | F | never (BRA and BSR use codes 0 and 1 of the branch opcodes) | 9 | VS | V = 1 |
| 2 | HI | C = 0 and Z = 0 (unsigned higher) | 10 | PL | N = 0 |
| 3 | LS | C = 1 or Z = 1 | 11 | MI | N = 1 |
| 4 | CC (HS) | C = 0 | 12 | GE | N = V |
| 5 | CS (LO) | C = 1 | 13 | LT | N ≠ V |
| 6 | NE | Z = 0 | 14 | GT | Z = 0 and N = V |
| 7 | EQ | Z = 1 | 15 | LE | Z = 1 or N ≠ V |
Control registers (MOVEC)
MOVEC moves a general register to or from one of these. The 12-bit code is the second word of the instruction. A code that the chosen model does
not have makes the decoder report an illegal control register.
| Code | Name | Models | What it is |
|---|---|---|---|
$000 | SFC | 68010 to 68060 | Source function code: the address space MOVES reads from. |
$001 | DFC | 68010 to 68060 | Destination function code. |
$002 | CACR | 68020 to 68060, ColdFire | Cache control. |
$003 | TC | 68040, 68060 | MMU translation control. |
$004 – $007 | ITT0 ITT1 DTT0 DTT1 | 68040, 68060 | Instruction and data transparent translation. On ColdFire the same codes are ACR0 to ACR3 (access control). |
$008 | BUSCR | 68060 | Bus control. |
$800 | USP | 68010 to 68060 | User stack pointer. |
$801 | VBR | 68010 to 68060, ColdFire | Vector base register: where the exception table starts (it is at 0 on the 68000). |
$802 | CAAR | 68020, 68030 | Cache address register. |
$803, $804 | MSP, ISP | 68020 to 68040 | Master and interrupt stack pointers. |
$805 – $807 | MMUSR URP SRP | 68040, 68060 | MMU status; user and supervisor root pointers. |
$808 | PCR | 68060 | Processor configuration. |
Exception vectors
An exception pushes the status register and PC (and on later models a format word) and loads the PC from a 32-bit vector: at address 4 * number on the 68000, at VBR + 4 * number from the 68010. The first entry is the
initial stack pointer, the second the initial PC: the cartridge header of a Mega Drive ROM starts with exactly this table.
| Vector | Address | Use |
|---|---|---|
| 0 | $000 | Initial stack pointer (reset) |
| 1 | $004 | Initial program counter (reset) |
| 2 | $008 | Bus error |
| 3 | $00C | Address error: a word or long access at an odd address, or a branch to one |
| 4 | $010 | Illegal instruction: every illegal or unavailable opcode, ILLEGAL, BKPT on the 68000 |
| 5 | $014 | Zero divide (DIVU, DIVS) |
| 6 | $018 | CHK, CHK2 |
| 7 | $01C | TRAPV, TRAPcc, FPU and MMU cpTRAPcc |
| 8 | $020 | Privilege violation |
| 9 | $024 | Trace |
| 10 | $028 | Line-A emulator: opcodes $A000 to $AFFF |
| 11 | $02C | Line-F emulator: opcodes $F000 to $FFFF that no coprocessor claims |
| 13, 14 | $034, $038 | Coprocessor protocol violation and format error (68020 and later) |
| 15 | $03C | Uninitialised interrupt vector |
| 24 | $060 | Spurious interrupt |
| 25 – 31 | $064 – $07C | Auto-vectored interrupts, level 1 to 7 |
| 32 – 47 | $080 – $0BC | TRAP #0 to TRAP #15 |
| 48 – 54 | $0C0 – $0D8 | FPU exceptions (branch on unordered, inexact, divide by zero, underflow, operand error, overflow, signalling NaN) |
| 56 – 58 | $0E0 – $0E8 | MMU exceptions (68030 and 68851) |
| 61 | $0F4 | 68060 unimplemented integer instruction (the software package handles MOVEP, CAS2 ...) |
| 64 – 255 | $100 – $3FC | User interrupt vectors, supplied by the interrupting device |
Not described
Known, not yet covered
- Reference: the exception stack frame formats of each model, the bus-error recovery frames, the 68040 and 68060 control-register bit layouts, the cache control register bits.