All of these are privileged. They are line-F opcodes (opcode map) and exist only on the models listed; elsewhere the opcode takes the line-F exception. The 68020 has no MMU of its own: it uses the external 68851 PMMU through coprocessor 0; the 68030 has the MMU on the chip with a subset of the 68851’s instructions; the 68040 and 68060 have a different MMU and different instructions.
68851 and 68030: coprocessor 0
Opcode $F000 | ea is followed by a command word. Its top three bits give the kind.
| Command word | Instruction | Models |
|---|---|---|
010 reg R FD 00000000 · 000 reg R FD ... · 011 000 R ... | PMOVE ea,reg and PMOVE reg,ea: reg is TC (translation control), SRP, CRP (root pointers, 64 bits) on the 68030 and 68851, TT0, TT1 (transparent translation, 68030), MMUSR (the status register, called PSR on the 68851), and on the 68851 also DRP, CAL, VAL, SCC, AC. Bit 9 is the direction (1 register to memory), bit 8 on the 68030 (FD) stops the translation cache being flushed (PMOVEFD). | 68030, 68851 |
001 000 R 0000 0 fc | PLOADR / PLOADW fc,ea: load a translation-cache entry for an address and function code. | 68030, 68851 |
001 mode mask fc | PFLUSHA (mode 001), PFLUSH fc,#mask (mode 100), PFLUSH fc,#mask,ea (mode 110). The function code fc is SFC, DFC, a data register (Dn) or an immediate 0–7. | 68030, 68851; 68040 and 68060 have their own |
100 level R A reg fc | PTESTR / PTESTW fc,ea,#level[,An]: walk the translation tables for an address, load MMUSR, and optionally put the last descriptor address in An. | 68030, 68851; 68040 below |
$F080 | cond, $F0C0 | cond | PBcc on a PMMU condition (BS BC LS LC SS SC AS AC WS WC IS IC GS GC CS CC) with a word or long displacement. | 68851 (and 68020 with it) |
$F048 | n + condition word | PDBcc, PScc, PTRAPcc. | 68851 |
$F100 | ea, $F140 | ea | PSAVE and PRESTORE the internal state of the 68851 (at a context switch). | 68851 |
The decoder shows a 68030 with only the first four; a 68020 with the MMU switched on gets all of them. The 68851-only instructions PVALID, PFLUSHR, PFLUSHS, PCMPW and the PMOVE forms for the 68851 task registers beyond the ones above are shown as reserved
command words. These encodings are written from the 68030 and 68851 user’s manuals as remembered; the only independent decoder available (Musashi’s) is too incomplete to check them, so this section is the least verified part of the decoder.
68040 and 68060
The 68040 replaced the coprocessor-0 forms with these:
| Opcode | Instruction | What it does |
|---|---|---|
$F500 | An · $F508 | An · $F510 · $F518 | PFLUSHN (An) · PFLUSH (An) · PFLUSHAN · PFLUSHA | Flush one page’s translation-cache entry (N: not the global ones) or all entries (PFLUSHAN: all but global ones). |
$F548 | An · $F568 | An | PTESTW (An) · PTESTR (An) | Search the tables for the address in An and load MMUSR. |
$F588 | An · $F5C8 | An | PLPAW (An) · PLPAR (An) (68060 only) | Translate a logical address to a physical one in An. |
The 68040 and 68060 have no PMOVE: their MMU is reached through the control registers TC, ITT0, ITT1, DTT0, DTT1, URP, SRP, MMUSR with MOVEC.
Cache instructions
| Opcode | Instruction | What it does |
|---|---|---|
1111 0100 cc 0 ss rrr | CINVL CINVP CINVA cache,(An) | Invalidate the cache line (ss = 01), page (10) or whole cache (11) holding the address in An. cc picks the data cache dc (01), instruction cache ic (10) or both bc (11); 00 is reserved. |
1111 0100 cc 1 ss rrr | CPUSHL CPUSHP CPUSHA | Write dirty data back, then invalidate. |
$F600 | An + long, $F620 | An + word | MOVE16 (Ax)+,(Ay)+ · (An)+,abs.l · abs.l,(An)+ · (An),abs.l · abs.l,(An) | Copy a 16-byte aligned line of memory without going through a register (the low four address bits are ignored). |
$F800 $01C0 + word | LPSTOP #n (68060) | Load the status register and stop in low-power mode until an interrupt. |
On a ColdFire, CPUSHL bc,(An) uses the same opcode as the 68040 and is described on the ColdFire page.
Sources
- MC68851 Paged Memory Management Unit User’s Manual and the MC68030 User’s Manual –
PMOVE,PFLUSH,PLOAD,PTEST - MC68040 User’s Manual and the MC68060 User’s Manual –
PFLUSH,PTEST,CINV,CPUSH,MOVE16,PLPA,LPSTOP
Not described
Known, not yet covered
- Reference: the translation-table descriptor formats, the layout of
TC,CRP,MMUSRand the transparent-translation registers; the 68851-only instructions listed above. - Viewer: the 68040 cache,
PFLUSH,PTESTandMOVE16forms were compared with Musashi (the opcode order ofPFLUSHwas wrong until it was); the coprocessor-0 forms were not.