The lines
The top four bits of the first word give the line. Within a line the fields are: ea the 6-bit effective address in bits 5–0,
Dn/An a register in bits 11–9, ss the size in bits 7–6 (00 byte, 01 word, 10 long). cond is the 4-bit
condition in bits 11–8.
| Line | Contents |
|---|---|
0 | Immediate arithmetic and logic (ORI, ANDI, SUBI, ADDI, EORI, CMPI), bit operations, MOVEP; 68010+: MOVES; 68020+: CMP2, CHK2, CAS, CAS2, CALLM, RTM |
1 2 3 | MOVE and MOVEA: byte (1), long (2), word (3) |
4 | Miscellaneous: NEGX, CLR, NEG, NOT, moves to and from SR and CCR, NBCD, SWAP, PEA, EXT, MOVEM, TST, TAS, ILLEGAL, TRAP, LINK, UNLK, MOVE USP, RESET, NOP, STOP, RTE, RTS, TRAPV, RTR, JSR, JMP, CHK, LEA; 68010+: MOVEC, RTD, BKPT; 68020+: 32-bit MUL and DIV, EXTB |
5 | ADDQ, SUBQ, Scc, DBcc; 68020+: TRAPcc |
6 | BRA, BSR, Bcc |
7 | MOVEQ |
8 | OR, DIVU, DIVS, SBCD; 68020+: PACK, UNPK |
9 | SUB, SUBA, SUBX |
A | Unassigned: the line-A emulator trap (vector 10). ColdFire: MOV3Q |
B | CMP, CMPA, CMPM, EOR |
C | AND, MULU, MULS, ABCD, EXG |
D | ADD, ADDA, ADDX |
E | Shifts and rotates; 68020+: bit-field instructions |
F | The coprocessor interface (68020 and later: FPU, MMU), 68040/68060 MOVE16, CINV, CPUSH, PFLUSH, PTEST, LPSTOP; otherwise the line-F emulator trap (vector 11) |
Line 0: immediate and bit operations
| Pattern (bits 15–0) | Instruction |
|---|---|
0000 000 0 ss ea, 0000 001 0 ss ea, 0000 101 0 ss ea | ORI, ANDI, EORI #imm,ea; with ea = $3C and size byte or word the target is CCR or SR |
0000 010 0 ss ea, 0000 011 0 ss ea, 0000 110 0 ss ea | SUBI, ADDI, CMPI |
0000 Dn 1 tt ea (ea mode not 1) | Dynamic bit operations BTST (tt = 0), BCHG, BCLR, BSET Dn,ea |
0000 100 0 tt ea + bit-number word | Static bit operations #n,ea |
0000 Dn 1 oo 001 An + displacement | MOVEP: oo = 0 word and 1 long from memory to Dn, 2 and 3 the reverse |
0000 111 0 ss ea + word (ss ≠ 3) | MOVES (68010+) |
0000 0ss 0 11 ea (ss = 0, 1, 2) + word | CMP2 / CHK2 (68020+) |
0000 1ss 0 11 ea (ss = 1, 2, 3) + word(s) | CAS; with ea = $3C and word or long size CAS2 (68020+) |
0000 0110 11 ea | RTM (ea mode 0 or 1) and CALLM (68020 only) |
Lines 1, 2, 3: MOVE
00 ss dest-reg dest-mode src-mode src-reg: the size is in bits 13–12 (01 byte, 11 word, 10 long), the destination field has its register and mode swapped. A destination mode 1 is
MOVEA (word or long only). The source extension words come first, then the destination’s.
Line 4: miscellaneous
| Pattern | Instruction |
|---|---|
0100 0000 ss ea · 0100 0010 ss ea · 0100 0100 ss ea · 0100 0110 ss ea | NEGX, CLR, NEG, NOT; with ss = 3: MOVE from SR, MOVE from CCR (68010+), MOVE to CCR, MOVE to SR |
0100 1000 00 ea · 0100 1000 0000 1 Rn | NBCD · LINK.L (68020+) |
0100 1000 0100 0 Dn · 0100 1000 0100 1 vvv · 0100 1000 01 ea | SWAP · BKPT (68010+) · PEA |
0100 1000 10 000 Dn · 0100 1000 11 000 Dn · 0100 1001 11 000 Dn | EXT.W · EXT.L · EXTB.L (68020+) |
0100 1d00 1s ea + register mask | MOVEM (d = 0 registers to memory, 1 memory to registers; s = 0 word, 1 long) |
0100 1010 ss ea · 0100 1010 11 ea · $4AFC | TST · TAS · ILLEGAL |
0100 1100 00 ea · 0100 1100 01 ea + word | MULU.L, MULS.L · DIVU.L, DIVS.L (68020+) |
0100 1110 0100 vvvv · 0100 1110 0101 0 An · 0100 1110 0101 1 An · 0100 1110 0110 d An | TRAP · LINK.W · UNLK · MOVE USP |
$4E70 $4E71 $4E72 $4E73 $4E74 $4E75 $4E76 $4E77 | RESET, NOP, STOP, RTE, RTD (68010+), RTS, TRAPV, RTR |
$4E7A, $4E7B + word | MOVEC (68010+): control register to and from a general register |
0100 1110 10 ea · 0100 1110 11 ea | JSR · JMP |
0100 Dn 1 10 ea · 0100 Dn 1 00 ea · 0100 An 1 11 ea | CHK.W · CHK.L (68020+) · LEA |
Line 5
0101 data 0/1 ss ea: ADDQ (bit 8 = 0) and SUBQ (1), with a 3-bit immediate 1 to 8 (0 means 8). With ss = 3: 0101 cond 11 ea is Scc; mode 1 is DBcc Dn,disp16; mode 7 with
register 2, 3, 4 is TRAPcc with a word, a long or no operand (68020+).
Line 6: branches
0110 cond disp8: condition 0 is BRA, 1 is BSR, 2 to 15 Bcc. A displacement byte of $00 means a 16-bit displacement follows; $FF means a 32-bit one follows on the
68020 and later (on the 68000 and 68010 it is just the displacement −1, an odd address). The target is the address of the first extension word (opcode address + 2) plus the displacement.
Line 7: MOVEQ
0111 Dn 0 data8: sign-extend the byte to 32 bits into Dn. With bit 8 set the opcode is illegal on the 68000 family; on ColdFire it is MVS / MVZ.
Line 8
1000 Dn opmode ea: opmodes 0–2 OR ea,Dn, 4–6 OR Dn,ea, 3 DIVU.W, 7 DIVS.W; opmode 4 with ea mode 0 or 1 is SBCD; opmodes 5 and 6 with mode 0 or 1 are
PACK and UNPK (68020+).
Lines 9 and D
1001 is SUB and 1101 is ADD: opmodes 0–2 to Dn, 4–6 to memory, 3 and 7 SUBA/ADDA (word, long); opmodes 4–6 with ea mode 0 or 1 are SUBX/ADDX.
Line A: the A-line trap
An opcode word that starts with $A is not an instruction on the 68000 family. It takes the line-A emulator exception (vector 10, address $028), and the program counter that is pushed points at the
opcode word, so a handler can read it: this is how classic Mac OS makes system calls. In the Mac’s convention bit 11 distinguishes a Toolbox trap (bit 11 set: number in bits 9–0, bit 10 the “auto-pop” flag) from
an OS trap (number in bits 7–0, flags in bits 10–8); the viewer says which in its notes but does not name the trap. The decoder shows the word as .aline $A123 with status reserved and a length of 2 bytes. On ColdFire the A-line also holds MOV3Q and the MAC unit’s instructions.
Line B
1011 Dn opmode ea: opmodes 0–2 CMP ea,Dn, 3 and 7 CMPA (word, long), 4–6 EOR Dn,ea, except that opmodes 4–6 with ea mode 1 are CMPM (Ay)+,(Ax)+.
Line C
1100 Dn opmode ea: opmodes 0–2 AND ea,Dn, 4–6 AND Dn,ea, 3 MULU.W, 7 MULS.W; opmode 4 with mode 0 or 1 is ABCD; 1100 Rx 1 01000 Ry is
EXG Dx,Dy, 1100 Rx 1 01001 Ry is EXG Ax,Ay and 1100 Dx 1 10001 Ay is EXG Dx,Ay.
Line E: shifts and rotates
1110 count/Dn dir ss i tt Dn: size ss (not 3), i = 0 immediate count 1–8 (0 means 8), 1 count in a data register; tt: 0 AS, 1 LS, 2 ROX, 3 RO; dir 0 right, 1 left. With ss = 3 and bit 11 clear:
1110 0tt d 11 ea, a one-bit shift of a memory word. With ss = 3 and bit 11 set: the bit-field instructions 1110 1ooo 11 ea (68020+): 0 BFTST, 1 BFEXTU, 2 BFCHG, 3 BFEXTS, 4 BFCLR,
5 BFFFO, 6 BFSET, 7 BFINS.
Line F
Bits 11–9 name the coprocessor. On the 68020 and 68030, coprocessor 1 is the 68881/68882 FPU and coprocessor 0 the MMU (68851, 68030); on the 68040 and 68060 coprocessor 1 is the on-chip FPU and
the cache and MMU instructions have their own encodings ($F4xx CINV and CPUSH, $F5xx PFLUSH and PTEST, $F6xx MOVE16). Bits 8–6 give the type: 0 general command, 1 cpScc/cpDBcc/cpTRAPcc, 2 and 3 cpBcc with a word or long displacement, 4 cpSAVE,
5 cpRESTORE.
Any other line-F word, or a coprocessor instruction with the FPU or MMU switched off or absent from the model, takes the line-F emulator exception (vector 11, address $02C); the decoder shows it as .fline $F123 with status reserved and a length of 2. Coprocessors 2 to 7 (user coprocessors) are shown the same way: only the coprocessor knows how long a
general command is.
Illegal opcodes
An opcode word that no instruction of the chosen model uses takes the illegal-instruction exception (vector 4). The CPU does not look at the words after it, so the decoder shows one word, .dc.w $xxxx. Two statuses: illegal when
no model of the family has it (a bad effective address for the instruction, MOVEA.B, a reserved field) and unavailable when a later model has it (the note says which instruction it is).
$4AFC is the exception: it is the instruction ILLEGAL.
Not described
Known, not yet covered
- Reference: a bit-by-bit grid of all 65,536 words; the Macintosh trap names.