The effective-address field
Most instructions end with a 6-bit effective address: a 3-bit mode in bits 5–3 and a 3-bit register in bits 2–0 of the opcode word. Mode 7 is not a mode but a group: its register field picks the mode. The words an effective address needs follow the opcode word (after any immediate operand), in the order the operands are written. The decoder writes operands as the manual does; the examples are real decodes (the bytes are the opcode word and its extension words).
| Mode | Reg | Name | Syntax | Extension | Example |
|---|---|---|---|---|---|
| 0 | 0–7 | Data register direct | Dn | none | 4A40 tst.w d0 |
| 1 | 0–7 | Address register direct | An | none | 5148 subq.w #8,a0 |
| 2 | 0–7 | Address register indirect | (An) | none | 4A10 tst.b (a0) |
| 3 | 0–7 | Postincrement | (An)+ | none | 1018 move.b (a0)+,d0 |
| 4 | 0–7 | Predecrement | -(An) | none | 2F00 move.l d0,-(a7) |
| 5 | 0–7 | Address register indirect with displacement | (d16,An) | 1 word: signed 16-bit displacement | 1028 FFFE move.b (-$2,a0),d0 |
| 6 | 0–7 | Address register indirect with index | (d8,An,Xn.size*scale), and on the 68020 and later ([bd,An,Xn],od) and the other full forms | 1 word (brief) or 1 to 5 words (full) | 1030 0004 move.b ($4,a0,d0.w),d0 |
| 7 | 0 | Absolute short | (xxx).w | 1 word, sign-extended to 32 bits | 1038 FFFF move.b $ffff.w,d0 |
| 7 | 1 | Absolute long | (xxx).l | 2 words | 2039 0001 0000 move.l $10000.l,d0 |
| 7 | 2 | Program counter with displacement | (d16,PC) | 1 word, relative to the address of that word | 4EBA 0010 jsr ($10,pc) |
| 7 | 3 | Program counter with index | (d8,PC,Xn), and the full forms on the 68020 and later | 1 to 5 words | 103B 0804 move.b ($4,pc,d0.l),d0 |
| 7 | 4 | Immediate | #data | byte and word: 1 word (a byte uses the low half); long: 2 words; FPU: 2, 3 or 3 words for double, extended, packed | 303C 1234 move.w #$1234,d0 |
Mode 7 with register 5, 6 or 7 does not exist; the opcode is then illegal. The forms that no operand-size or category allows are illegal too.
Categories
Each instruction names which modes it accepts by category. The decoder rejects an opcode whose mode is outside its category (it is then an illegal opcode of one word).
| Category | Modes | Used by |
|---|---|---|
| Data | all except An | sources of OR, AND, MULU, DIVU, CHK; byte sources of ADD and SUB |
| Memory | all except Dn and An | destinations of OR Dn,<ea>, AND Dn,<ea>, ADD Dn,<ea>, shifts of memory |
| Control | (An), (d16,An), (d8,An,Xn), abs.w, abs.l, (d16,PC), (d8,PC,Xn) | LEA, PEA, JMP, JSR |
| Alterable | all except (d16,PC), (d8,PC,Xn) and immediate | destinations |
| Data alterable | alterable except An | destinations of MOVE, CLR, NEG, NOT, Scc, TAS, NBCD and of TST on the 68000 and 68010 |
| Memory alterable | data alterable except Dn | MOVES, CAS, shifts of memory |
The 68020 relaxed a few: TST accepts An, immediate and the PC-relative modes; the 68010 and later let CMPI use the two PC-relative modes.
The brief index extension word
Mode 6 and (d8,PC,Xn) take one word, in this layout on every model:
| Bits | Field |
|---|---|
| 15 | D/A: 0 data register, 1 address register as the index |
| 14–12 | Index register number |
| 11 | W/L: 0 the low word of the index register, sign-extended; 1 the whole register |
| 10–9 | Scale: 0 ×1, 1 ×2, 2 ×4, 3 ×8. Only the 68020 and later and ColdFire have it; on the 68000 and 68010 these bits are ignored (the manual says they are zero) and the decoder notes it |
| 8 | 0 for the brief word. On the 68020 and later a 1 here makes it the full word below; on the 68000, 68010 and ColdFire the bit is ignored |
| 7–0 | Signed 8-bit displacement |
The effective address is An + (sign-extended) d8 + index * scale; for (d8,PC,Xn) the base is the address of the extension word. Written ($4,a0,d0.w*4).
The full index extension word (68020 and later)
With bit 8 set, the word is followed by an optional base displacement and an optional outer displacement:
| Bits | Field |
|---|---|
| 15–9 | Index register, size and scale, as in the brief word |
| 8 | 1: the full format |
| 7 | BS, base suppress: the address register (or PC) is not added |
| 6 | IS, index suppress: no index register |
| 5–4 | BD SIZE: 0 reserved, 1 null (no word), 2 a word, 3 a long word of base displacement |
| 3 | 0 (must be zero) |
| 2–0 | I/IS, the indirection: see the table below |
IS | I/IS | Form | Outer displacement |
|---|---|---|---|
| 0 | 000 | no memory indirection: (bd,An,Xn*s) | none |
| 0 | 001, 010, 011 | pre-indexed memory indirect: ([bd,An,Xn*s],od) | null, word, long |
| 0 | 100 | reserved | |
| 0 | 101, 110, 111 | post-indexed memory indirect: ([bd,An],Xn*s,od) | null, word, long |
| 1 | 000 | no memory indirection, no index: (bd,An) | none |
| 1 | 001, 010, 011 | memory indirect without an index: ([bd,An],od) | null, word, long |
| 1 | 100 to 111 | reserved |
The words follow in this order: the extension word, the base displacement, the outer displacement. A suppressed base register is written zpc for the PC and left out for an An. When
everything is suppressed the decoder writes (0). The reserved combinations are shown as an illegal opcode with the reason. Examples:
2030 0170 1234 5678 move.l ($12345678,a0),d0; 2030 0171 1234 5678 move.l ([$12345678,a0]),d0;
2030 0126 1234 5678 move.l ([$1234,a0],d0.w,$5678),d0; 2030 0410 move.l ($10,a0,d0.w*4),d0.
The longest instruction is MOVE.L with two full-format operands, each with a 32-bit base and outer displacement: 22 bytes.
How the decoder writes them
The default is the manual’s own notation (as above, lower case). The GNU-assembler MIT notation is an option (approximate): %a0@(4,%d0:w:4) for (4,a0,d0.w*4),
%a0@+, %a0@-, 0x1234:w for an absolute short, a size attached to the mnemonic (movew). The viewer replaces an absolute operand by a name when it has one for that address
($C00004 is vdp_control in a Mega Drive ROM).
Not described
Known, not yet covered
- Reference: the extra memory-access cost of each mode (cycle counts); the exact address-error rules for odd addresses.