68000 Instruction Set: integer instructions

Operands: ea an effective address; Dn An registers; #n an immediate. Sizes: .b byte, .w word, .l long word. Flags lists the condition codes the instruction can change (X N Z V C; “none” when it changes none); an instruction that reads X or the condition is said so. The status of an instruction is always documented on the 68000 unless a note says it is a later model’s (those are on 68010 to 68060 additions). Cycle counts are not given. Instructions marked privileged take the privilege-violation exception in user mode.

Data movement

Mnemonic	Forms	Sizes	Flags	What it does
`MOVE`	`ea,ea`	b w l	N Z V C (V and C cleared)	Copy the source to a data-alterable destination.
`MOVEA`	`ea,An`	w l	none	Copy to an address register; a word is sign-extended.
`MOVEQ`	`#n,Dn`	l	N Z V C	Load an 8-bit signed value, sign-extended to 32 bits.
`MOVEM`	`list,ea` · `ea,list`	w l	none	Move several registers to or from consecutive memory. The mask word follows the opcode; for `-(An)` its bits are reversed (bit 0 is A7). A word load sign-extends each register.
`MOVEP`	`Dn,(d16,An)` · `(d16,An),Dn`	w l	none	Move alternate bytes (for 8-bit peripherals on a 16-bit bus). Emulated on the 68060.
`MOVE from SR`	`SR,ea`	w	none	Copy the status register. Privileged from the 68010.
`MOVE to CCR`	`ea,CCR`	w	X N Z V C	Load the condition codes from the low byte of the source.
`MOVE to SR`	`ea,SR`	w	X N Z V C and the system byte	Load the status register. Privileged.
`MOVE USP`	`An,USP` · `USP,An`	l	none	Copy to or from the user stack pointer. Privileged.
`EXG`	`Dx,Dy` · `Ax,Ay` · `Dx,Ay`	l	none	Exchange two registers.
`LEA`	`ea,An`	l	none	Load the effective address (control modes only).
`PEA`	`ea`	l	none	Push the effective address on the stack.
`LINK`	`An,#d16` (and `.l` from the 68020)	w l	none	Push `An`, copy `A7` into it, then add the displacement to `A7`: a stack frame.
`UNLK`	`An`		none	Copy `An` to `A7` and pop `An`.
`SWAP`	`Dn`	w	N Z V C	Exchange the two halves of a data register.
`EXT`	`Dn`	w l	N Z V C	Sign-extend a byte to a word, or a word to a long word.

Arithmetic

Mnemonic	Forms	Sizes	Flags	What it does
`ADD`	`ea,Dn` · `Dn,ea`	b w l	X N Z V C	Add.
`ADDA`	`ea,An`	w l	none	Add to an address register; a word source is sign-extended.
`ADDI`	`#n,ea`	b w l	X N Z V C	Add an immediate value.
`ADDQ`	`#1..8,ea`	b w l	X N Z V C (none for `An`)	Add a 3-bit value. On an address register the whole register changes and no flag does.
`ADDX`	`Dy,Dx` · `-(Ay),-(Ax)`	b w l	X N Z V C (reads X, Z)	Add with the extend bit.
`SUB`	`ea,Dn` · `Dn,ea`	b w l	X N Z V C	Subtract.
`SUBA`	`ea,An`	w l	none	Subtract from an address register.
`SUBI`	`#n,ea`	b w l	X N Z V C	Subtract an immediate value.
`SUBQ`	`#1..8,ea`	b w l	X N Z V C (none for `An`)	Subtract a 3-bit value.
`SUBX`	`Dy,Dx` · `-(Ay),-(Ax)`	b w l	X N Z V C (reads X, Z)	Subtract with the extend bit.
`NEG`	`ea`	b w l	X N Z V C	Negate (0 minus the operand).
`NEGX`	`ea`	b w l	X N Z V C (reads X, Z)	Negate with the extend bit.
`CLR`	`ea`	b w l	N Z V C (N, V, C cleared, Z set)	Clear to zero. The 68000 reads the destination first.
`CMP`	`ea,Dn`	b w l	N Z V C	Compare: `Dn` minus the source; only the flags change.
`CMPA`	`ea,An`	w l	N Z V C	Compare with an address register (a word source is sign-extended).
`CMPI`	`#n,ea`	b w l	N Z V C	Compare with an immediate value. From the 68010 the PC-relative modes are allowed.
`CMPM`	`(Ay)+,(Ax)+`	b w l	N Z V C	Compare two memory operands and advance both pointers.
`TST`	`ea`	b w l	N Z V C (V, C cleared)	Compare with zero. The 68020 and later accept `An`, immediate and PC-relative operands.
`MULS`	`ea,Dn`	w	N Z V C	Signed 16 × 16 to 32 bits. 68020 and later also have the long forms (extensions).
`MULU`	`ea,Dn`	w	N Z V C	Unsigned 16 × 16 to 32 bits.
`DIVS`	`ea,Dn`	w	N Z V C	Signed 32 ÷ 16: the quotient in the low word, the remainder in the high word. Division by zero takes vector 5; overflow sets V and leaves `Dn`.
`DIVU`	`ea,Dn`	w	N Z V C	Unsigned 32 ÷ 16.
`ABCD`	`Dy,Dx` · `-(Ay),-(Ax)`	b	X Z C (reads X, Z)	Add packed decimal bytes with the extend bit.
`SBCD`	`Dy,Dx` · `-(Ay),-(Ax)`	b	X Z C (reads X, Z)	Subtract packed decimal bytes.
`NBCD`	`ea`	b	X Z C (reads X, Z)	Negate a packed decimal byte.

Logic, bit operations, shifts

Mnemonic	Forms	Sizes	Flags	What it does
`AND`	`ea,Dn` · `Dn,ea`	b w l	N Z V C	AND.
`ANDI`	`#n,ea`	b w l	N Z V C	AND with an immediate value.
`OR`	`ea,Dn` · `Dn,ea`	b w l	N Z V C	OR.
`ORI`	`#n,ea`	b w l	N Z V C	OR with an immediate value.
`EOR`	`Dn,ea`	b w l	N Z V C	Exclusive OR.
`EORI`	`#n,ea`	b w l	N Z V C	Exclusive OR with an immediate value.
`NOT`	`ea`	b w l	N Z V C	Invert every bit.
`ORI to CCR`	`#n,CCR`	b	X N Z V C	OR into the condition codes.
`ANDI to CCR`	`#n,CCR`	b	X N Z V C	AND into the condition codes.
`EORI to CCR`	`#n,CCR`	b	X N Z V C	Exclusive OR into the condition codes.
`ORI to SR`	`#n,SR`	w	all	OR into the status register. Privileged.
`ANDI to SR`	`#n,SR`	w	all	AND into the status register. Privileged.
`EORI to SR`	`#n,SR`	w	all	Exclusive OR into the status register. Privileged.
`BTST`	`Dn,ea` · `#n,ea`	b (memory) l (register)	Z	Test a bit: Z = 1 if it was 0. The bit number is taken modulo 8 for memory and 32 for a register.
`BCHG`	`Dn,ea` · `#n,ea`	b l	Z	Test a bit, then invert it.
`BCLR`	`Dn,ea` · `#n,ea`	b l	Z	Test a bit, then clear it.
`BSET`	`Dn,ea` · `#n,ea`	b l	Z	Test a bit, then set it.
`TAS`	`ea`	b	N Z V C	Test the byte and set its top bit, in one indivisible bus cycle.
`ASL`	`#1..8,Dn` · `Dn,Dn` · `ea` (word)	b w l	X N Z V C	Arithmetic shift left; V is set if the sign changed at any point.
`ASR`	as `ASL`	b w l	X N Z V C (V cleared)	Arithmetic shift right, keeping the sign.
`LSL`	as `ASL`	b w l	X N Z V C (V cleared)	Logical shift left.
`LSR`	as `ASL`	b w l	X N Z V C (V cleared)	Logical shift right.
`ROXL`	as `ASL`	b w l	X N Z V C (reads X)	Rotate left through the extend bit.
`ROXR`	as `ASL`	b w l	X N Z V C (reads X)	Rotate right through the extend bit.
`ROL`	as `ASL`	b w l	N Z V C	Rotate left.
`ROR`	as `ASL`	b w l	N Z V C	Rotate right.

A shift with a count in a register uses the count modulo 64. A shift of memory moves a word by one bit.

Program control and exceptions

Mnemonic	Forms	Sizes	Flags	What it does
`BRA`	`label`	s w (l)	none	Branch always. The displacement is 8 bits in the opcode, or 16 in the next word, or 32 from the 68020.
`BSR`	`label`	s w (l)	none	Push the address of the next instruction and branch.
`Bcc`	`label`	s w (l)	reads the flags	Branch if the condition holds: `BHI BLS BCC BCS BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE`.
`DBcc`	`Dn,label`	w	reads the flags	If the condition is false, decrement the low word of `Dn` and branch unless it became −1. `DBF` is written `DBRA`.
`Scc`	`ea`	b	reads the flags	Set the byte to `$FF` if the condition is true, else `$00`.
`JMP`	`ea`		none	Jump to the effective address (control modes).
`JSR`	`ea`		none	Push the return address and jump.
`RTS`			none	Pop the return address.
`RTR`			X N Z V C	Pop the condition codes, then the return address.
`RTE`			all	Return from exception: pop the status register and PC (and a format word on the 68010 and later). Privileged.
`TRAP`	`#0..15`		none	Take exception vector 32 + n.
`TRAPV`			reads V	Take vector 7 if V is set.
`CHK`	`ea,Dn`	w (l from the 68020)	N (others undefined)	Take vector 6 if `Dn` is negative or above the operand.
`ILLEGAL`			none	Take the illegal-instruction exception. Opcode `$4AFC`.
`NOP`			none	Do nothing and wait for the pipeline to drain.
`STOP`	`#n`		all	Load the status register from the immediate word and stop until an interrupt or reset. Privileged.
`RESET`			none	Assert the RESET pin for external devices. Privileged.

Sources

M68000 Family Programmer’s Reference Manual – Motorola/NXP: each instruction’s forms, sizes and condition codes

Not described

Known, not yet covered

Reference: cycle counts for each instruction and addressing mode; the exact V and C rules of each shift and the undefined condition codes after ABCD, SBCD, NBCD, DIVx and CHK; operand-size and mode limits of the ColdFire revisions (see ColdFire).

68000 Instruction Set – Integer instructions