On a model that does not have an instruction the opcode word takes the illegal-instruction exception, and the viewer shows it as one .dc.w word with the status unavailable, naming the instruction it would be.
Models lists where each exists. Columns and conventions are those of Integer instructions.
68010 and later
| Mnemonic | Forms | Models | Flags | What it does |
|---|---|---|---|---|
MOVEC | Rc,Rn · Rn,Rc | 68010+, ColdFire | none | Move a control register to or from a general register; the second word holds the register and the control register number. Privileged. |
MOVES | Rn,ea · ea,Rn | 68010+ | none | Move a byte, word or long to or from the address space the function-code registers DFC and SFC select (memory alterable modes). Privileged. |
MOVE from CCR | CCR,ea | 68010+ | none | Copy the condition codes: the unprivileged replacement for MOVE from SR, which is privileged from the 68010 on. |
RTD | #d16 | 68010+ | none | Return and deallocate: pop the PC, then add the displacement to A7. |
BKPT | #0..7 | 68010+ | none | Breakpoint: a breakpoint-acknowledge cycle, then the illegal-instruction exception. |
The 68010 also adds the loop mode (a DBcc loop of one instruction runs from the instruction buffer) and the VBR; neither is visible in the opcode.
68020 and later
| Mnemonic | Forms | Models | Flags | What it does |
|---|---|---|---|---|
BFTST | ea{off:width} | 68020 to 68060 | N Z V C | Test a bit field: N is its top bit, Z set if all zero; V and C cleared. See the field format below. |
BFEXTU | ea{off:width},Dn | 68020 to 68060 | N Z V C | Extract a bit field, zero-extended, into Dn. |
BFEXTS | ea{off:width},Dn | 68020 to 68060 | N Z V C | Extract a bit field, sign-extended. |
BFFFO | ea{off:width},Dn | 68020 to 68060 | N Z V C | Find the first set bit in a field: Dn gets its position (the offset plus the width if none). |
BFCHG | ea{off:width} | 68020 to 68060 | N Z V C | Test, then invert the field (control-alterable modes and Dn). |
BFCLR | ea{off:width} | 68020 to 68060 | N Z V C | Test, then clear the field. |
BFSET | ea{off:width} | 68020 to 68060 | N Z V C | Test, then set the field. |
BFINS | Dn,ea{off:width} | 68020 to 68060 | N Z V C | Insert the low bits of Dn into the field. |
CAS | Dc,Du,ea | 68020 to 68060 | N Z V C | Compare Dc with the memory operand; if equal store Du, otherwise load the operand into Dc: an atomic read-modify-write. |
CAS2 | Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) | 68020 to 68040 (software on the 68060) | N Z V C | The same on two memory operands at once. |
CMP2 | ea,Rn | 68020 to 68040 (software on the 68060) | Z C | Compare a register with a lower and an upper bound stored at the effective address (control modes). |
CHK2 | ea,Rn | 68020 to 68040 (software on the 68060) | Z C | As CMP2, then take vector 6 if out of bounds. |
DIVU.L | ea,Dq · ea,Dr:Dq · DIVUL.L ea,Dr:Dq | 68020 to 68060 (the 64-bit form is software on the 68060) | N Z V C | Unsigned 32 ÷ 32 (Dq), or with a remainder in Dr (DIVUL), or 64 ÷ 32 when the form is Dr:Dq with the 64-bit size bit set. |
DIVS.L | as DIVU.L | as DIVU.L | N Z V C | Signed. The long MULU.L and MULS.L (ea,Dl or ea,Dh:Dl, 32 × 32 to 32 or to 64 bits) use the same extension word with different bits and are listed under MULU and MULS. |
EXTB | Dn | 68020+ | N Z V C | Sign-extend a byte to a long word. |
PACK | Dx,Dy,#adj · -(Ax),-(Ay),#adj | 68020+ | none | Pack two unpacked BCD digits into a byte after adding the adjustment word. |
UNPK | same | 68020+ | none | Unpack a byte into two digits, adding the adjustment. |
TRAPcc | .w #n · .l #n · none | 68020+, ColdFire TPF | reads the flags | Take vector 7 if the condition is true; an optional 16- or 32-bit operand follows for the handler. |
CALLM | #args,ea | 68020 only | none | Call a module: push a module frame. Dropped from the 68030. |
RTM | Rn | 68020 only | X N Z V C | Return from a module. |
LINK.L, CHK.L, TST and CMPI forms | 68020+ (CMPI PC-relative: 68010+) | Described with the 68000 instructions of the same name in Integer instructions. |
The bit-field extension word
Every bit-field instruction takes one extension word: 0 Dn Do offset Dw width. Bits 14–12 are the data register (for BFEXTU, BFEXTS, BFFFO and BFINS; zero otherwise), bit 11 (Do) says
the offset in bits 10–6 is a data register number (when set) or a number 0 to 31, bit 5 (Dw) the same for the width in bits 4–0 (0 means 32). The decoder writes ea{4:8}, ea{d1:d2}. A register offset is signed and may reach 2 GB either side of the operand address; for Dn as the operand the offset is modulo 32.
The 68060
The 68060 does not execute these instructions in hardware: the unimplemented-integer-instruction exception (vector 61) calls a software package. The decoder shows them as documented and marks them emulated in the notes:
MOVEP, CAS2, CHK2, CMP2, the 64-bit forms of MULU.L, MULS.L, DIVU.L, DIVS.L. CALLM and RTM do not exist after the 68020. The 68060 adds LPSTOP (see MMU and caches) and PLPA.
This list is written from the MC68060 user’s manual as remembered and has not been checked against an emulator.
Not described
Known, not yet covered
- Reference: the 68010 exception stack frame and the loop-mode conditions; the module descriptor format of
CALLM; the exact flag results ofCAS,CMP2and the bit-field instructions in each edge case; cycle counts.