The FPU and how it is reached
The 68881 and 68882 are coprocessors: the 68020 and 68030 hand them every line-F opcode whose coprocessor field (bits 11–9) is 1, over the coprocessor interface. The 68040 and 68060 contain the unit. The instructions are
$F200 to $F3FF: bits 8–6 select the kind (general command 0, FScc/FDBcc/FTRAPcc 1, FBcc with a word or long displacement 2 and 3,
FSAVE 4, FRESTORE 5). A general command is followed by a 16-bit command word, then the effective-address words. With the FPU switched off in the decoder, or on a 68000 or 68010, they take the
line-F exception.
Registers: FP0 to FP7, 80 bits each (sign, 15-bit exponent, 64-bit mantissa); FPCR (exception enables, rounding precision and mode), FPSR (condition codes N Z I NaN in bits 27–24, quotient byte, exception and accrued-exception bytes), FPIAR (the address of the last instruction).
The decoder lists fpsr among the registers a floating-point operation writes; it does not change the integer condition codes.
Data formats
| Code | Suffix | Format | Immediate size |
|---|---|---|---|
| 0 | .l | 32-bit integer | 2 words |
| 1 | .s | single precision (32 bits) | 2 words |
| 2 | .x | extended precision (96 bits stored, 80 used) | 6 words |
| 3 | .p | packed decimal (96 bits): the k-factor sits in the command word of a store | 6 words |
| 4 | .w | 16-bit integer | 1 word |
| 5 | .d | double precision (64 bits) | 4 words |
| 6 | .b | 8-bit integer | 1 word (the low byte) |
| 7 | .p | packed decimal with the k-factor in a data register (stores only) |
The decoder shows an immediate floating-point operand as its raw hexadecimal words (#$3f800000 is the single 1.0).
The command word
A command word that no row below defines (class 001, an opmode that does not exist on the model, a mode the operation does not allow) makes the 68881 report a protocol violation; the decoder shows it as a reserved word of one opcode word and says why.
| Bits 15–13 | Meaning | Form |
|---|---|---|
000 | register to register | F<op>.x FPm,FPn: source in bits 12–10, destination 9–7, operation 6–0 |
010 | memory (or Dn) to register | F<op>.fmt ea,FPn: format in bits 12–10. With format code 7: FMOVECR |
011 | register to memory | FMOVE.fmt FPn,ea (packed: with {#k} or {Dn}) |
100, 101 | control registers to and from ea | FMOVE.L ea,FPCR, FMOVEM.L ea,FPCR/FPSR/FPIAR (bits 12–10 select the registers: 100 FPCR, 010 FPSR, 001 FPIAR) |
110, 111 | data registers to and from memory | FMOVEM.X ea,list / FMOVEM.X list,ea: mode bits 12–11 give a static or dynamic (Dn) list and, for stores, the predecrement order |
001 | reserved | The decoder shows the word as reserved. |
Operations
The opmode is bits 6–0 of the command word. A row is available on every model with an FPU unless Hardware says otherwise: on the 68040 and 68060, only the rows marked yes run in hardware; the others take the unimplemented-instruction exception and are emulated by Motorola’s floating-point software package (the decoder marks them emulated).
| Mnemonic | Opmode | Hardware (68040/060) | What it does |
|---|---|---|---|
FMOVE | $00 | yes | Copy (and convert) the source to the destination register; also the store and control-register forms above. |
FINT | $01 | yes | Round to an integer using the FPCR rounding mode. |
FSINH | $02 | no | Hyperbolic sine. |
FINTRZ | $03 | yes | Round to an integer, towards zero. |
FSQRT | $04 | yes | Square root. |
FLOGNP1 | $06 | no | ln(x + 1). |
FETOXM1 | $08 | no | ex − 1. |
FTANH | $09 | no | Hyperbolic tangent. |
FATAN | $0A | no | Arc tangent. |
FASIN | $0C | no | Arc sine. |
FATANH | $0D | no | Inverse hyperbolic tangent. |
FSIN | $0E | no | Sine. |
FTAN | $0F | no | Tangent. |
FETOX | $10 | no | ex. |
FTWOTOX | $11 | no | 2x. |
FTENTOX | $12 | no | 10x. |
FLOGN | $14 | no | Natural logarithm. |
FLOG10 | $15 | no | Base-10 logarithm. |
FLOG2 | $16 | no | Base-2 logarithm. |
FABS | $18 | yes | Absolute value. |
FCOSH | $19 | no | Hyperbolic cosine. |
FNEG | $1A | yes | Negate. |
FACOS | $1C | no | Arc cosine. |
FCOS | $1D | no | Cosine. |
FGETEXP | $1E | no | Extract the exponent as a number. |
FGETMAN | $1F | no | Extract the mantissa. |
FDIV | $20 | yes | Destination divided by the source. |
FMOD | $21 | no | Modulo, rounded towards zero. |
FADD | $22 | yes | Add. |
FMUL | $23 | yes | Multiply. |
FSGLDIV | $24 | no | Divide to single precision. |
FREM | $25 | no | IEEE remainder. |
FSCALE | $26 | no | Scale by a power of two. |
FSGLMUL | $27 | no | Multiply to single precision. |
FSUB | $28 | yes | Subtract. |
FSINCOS | $30–$37 | no | Sine and cosine at once: FSINCOS src,FPc:FPs, the cosine register in the opmode’s low three bits. |
FCMP | $38 | yes | Compare the destination with the source (FPSR condition codes only). |
FTST | $3A | yes | Compare with zero. |
FMOVECR | command 010 111 | no | FMOVECR #offset,FPn: load a constant (π, e, log constants, powers of ten) from the coprocessor’s ROM; the offset is in bits 6–0. |
FSMOVE, FDMOVE | $40, $44 | 68040, 68060 only | Move, rounded to single or double precision. |
FSSQRT FDSQRT, FSABS FDABS, FSNEG FDNEG | $41 $45, $58 $5C, $5A $5E | 68040, 68060 only | Square root, absolute value, negate, rounded to single or double. |
FSDIV FDDIV, FSADD FDADD, FSMUL FDMUL, FSSUB FDSUB | $60 $64, $62 $66, $63 $67, $68 $6C | 68040, 68060 only | Divide, add, multiply, subtract, rounded to single or double. |
On the 68020 and 68030 the single/double-rounding opmodes ($40 and above) do not exist: the command word is reserved there, and the decoder says so.
FMOVEM
FMOVEM.X list,ea and ea,list move several extended-precision registers; the list is a mask in the low eight bits (for -(An) bit 7 is FP7, otherwise bit 7 is FP0) or a data register holding it (dynamic).
FMOVEM.L ea,FPCR/FPSR/FPIAR moves control registers, any combination, in the order FPCR, FPSR, FPIAR; a single control register is written FMOVE.L.
Conditions and branches
FBcc branches on a condition of the FPSR flags (N Z I NaN), with a 16-bit or 32-bit displacement: opcode $F280 | cond (word), $F2C0 | cond (long). FNOP is FBF with displacement zero ($F280 $0000).
FDBcc Dn,label ($F248 | n then the condition word and a 16-bit displacement), FScc ea ($F240 | ea then the condition word) and FTRAPcc ($F27A word operand, $F27B long, $F27C none) test the same conditions.
On the 68040 and 68060 these three are emulated in software.
| Codes 0–15 | Codes 16–31 (the same test, and a signalling NaN raises an exception) |
|---|---|
F EQ OGT OGE OLT OLE OGL OR UN UEQ UGT UGE ULT ULE NE T | SF SEQ GT GE LT LE GL GLE NGLE NGL NLE NLT NGE NGT SNE ST |
The letters are: O ordered, U unordered, G greater, L less, E equal, N not, T true, F false. A predicate of 32 or above is reserved.
FSAVE and FRESTORE
FSAVE ea ($F300 | ea: control alterable and predecrement) writes the internal state of the unit and FRESTORE ea ($F340 | ea: control and postincrement) loads it: operating systems use them at a context switch.
Both are privileged. FRESTORE does not take an immediate operand.
On the 68040 and 68060
The on-chip unit executes the rows marked yes above. The rest of the 68881 set and FMOVEM to and from memory with unusual list forms, packed decimal conversion, FDBcc, FScc and FTRAPcc take the F-line (unimplemented
floating-point) exception and are handled by Motorola’s software package; the viewer shows them with the ordinary mnemonic and the note. The rounding-precision opmodes (FSADD, FDMUL and so on) exist only here.
Sources
- MC68881/MC68882 Floating-Point Coprocessor User’s Manual – the command word, opmodes, conditions
- MC68040 User’s Manual – the on-chip unit, its rounding-precision opmodes and the list of software-emulated operations
Not described
Known, not yet covered
- Reference: the effect of each operation on the FPSR condition codes and exception bits; the FPCR bit layout; the table of the 22 constants of
FMOVECR; the packed-decimal format; the FSAVE state frames. - Viewer: checked against Musashi only for the 68040 form of the instructions (Musashi decodes no 68881 form); the 68060’s software-emulated list was written from the manual as remembered.