Xtensa Registers

Introduction

An Xtensa program sees sixteen address registers and the register files of the options its core has. The program counter is not a numbered register: it is read only by call and branch instructions, and it is not an operand.

Address registers a0 to a15

Sixteen 32-bit registers, named a0 to a15 by a 4-bit field. With the Windowed Register option they are a window onto 64 physical registers (see windowed registers); without it (the ESP8266) they are the physical registers. By software convention a0 is the return address and a1 the stack pointer; the explorer can write a1 as sp.

Register	Windowed ABI	Call0 ABI
`a0`	Return address (with the window increment in its top 2 bits)	Return address
`a1`	Stack pointer	Stack pointer
`a2` to `a7`	Arguments and the return value (a2)	Arguments and the return value (a2 to a5 are return registers for larger values)
`a8` to `a15`	Locals; the callee's window overlays the top ones	`a12` to `a15` are callee-saved, the rest are scratch

Other register files

Registers	Option and chips	What they are
`b0` to `b15`	Boolean; ESP32, ESP32-S3	One-bit registers (the special register `BR`) for compare results and conditional moves.
`f0` to `f15`	Floating point; ESP32, ESP32-S3	32-bit single-precision registers; with `FCR` and `FSR`.
`m0` to `m3`, `ACC`	MAC16; ESP32, ESP32-S3	Four 32-bit multiplier operands and a 40-bit accumulator.
`q0` to `q7`, `QACC`, `ACCX`	PIE; ESP32-S3	128-bit vector registers and accumulators.
special registers	all	The special registers: PS, SAR, WINDOWBASE and the rest.
user registers	all	The user registers: THREADPTR, FCR, FSR and the extension state.

Not described

Known, not yet covered

Reference: the exact calling-convention rules for structures, varargs and floating point.

Unknown

Reference: the ABI table is from the common compiler convention as remembered; no document was open.