Introduction
Xtensa is configured per chip. The table says which options each ESP chip's core has. The ESP32, ESP32-S2 and ESP32-S3 columns are what the
Espressif toolchain's objdump for that chip decodes (the toolchain selects each chip's configuration with a wrapper); the ESP32 and ESP32-S3
were also read from Tensilica's own configuration files (XCHAL_HAVE_*), and the ESP8266 only from its configuration file.
The ESP32-C2, C3, C6, H2 and P4 use RISC-V and are on the RISC-V pages.
Options by chip
| Option | ESP8266 (LX106) | ESP32 (LX6) | ESP32-S2 (LX7) | ESP32-S3 (LX7) |
|---|---|---|---|---|
| Code Density (16-bit) | yes | yes | yes | yes |
| Windowed registers (64 physical) | no (16 registers, call0 ABI) | yes | yes | yes |
| Loops | no | yes | no | yes |
| Booleans | no | yes | no | yes |
| MAC16 | no | yes | no | yes |
| MUL16, MULL | yes | yes | yes | yes |
| MULUH, MULSH | no | yes | yes | yes |
| QUOS, QUOU, REMS, REMU | no | yes | yes | yes |
| MIN, MAX, CLAMPS, SEXT | no | yes | yes | yes |
| NSA, NSAU | yes | yes | yes | yes |
| L32AI, S32RI | no | yes | yes | yes |
| S32C1I (and SCOMPARE1) | no | yes | no | yes |
| Single-precision FPU | no | yes | no | yes |
| F64 and EXPSTATE (Espressif) | no | yes | no | no |
| SALT, SALTU | no | no | yes | yes |
| GPIO instructions | no | no | yes (S2 form) | as EE.* in PIE |
| Vector (PIE) instructions | no | no | no | yes |
| THREADPTR | no | yes | yes | yes |
| Special registers: epc, eps, excsave | levels 1 to 3 | levels 1 to 7 | levels 1 to 7 | levels 1 to 7 |
| Cache and MMU instructions | no | no | no | no |
What an ELF file says about the chip
Nothing directly. The ESP toolchains write e_machine 94 and e_flags 0x300 (EF_XTENSA_XT_INSN and
EF_XTENSA_XT_LIT, both "the linker may relax instructions and literals"); the machine field of e_flags (EF_XTENSA_MACH, the
low four bits) is 0 for every ESP chip. A .xtensa.info note holds the ABI (0 windowed, 1 call0) and
USE_ABSOLUTE_LITERALS. So the explorer's Mode choice is how you say which chip, and "From the file" means the ESP32.
How the decoder was compared
Each chip's objdump was run over a raw binary with every word placed at a fixed 8-byte stride (padding that decodes in whole
instructions, so a rejected word cannot throw the next one out of step) and the lines matched by address. The words: every 24-bit word of
op0 0 to 7 (all 220 words of each), every 16-bit word of op0 8 to 13, and 4096 words of each of op0 14 and 15
(on the ESP32-S3, 40,000 random 32-bit words of each). Texts are compared after collapsing white space; lengths are compared too.
| Chip | Words compared | Same | Explained | Unexplained |
|---|---|---|---|---|
| ESP32 | 8,421,376 | 5,912,245 | 2,509,131 | 0 |
| ESP32-S2 | 8,421,376 | 5,252,085 | 3,169,291 | 0 |
| ESP32-S3 | 8,493,184 | 6,487,773 | 2,005,411 | 0 |
| ESP8266 | no objdump for this core; compared with Tensilica's configuration file: 117 opcode encodings and 30 special registers, no difference. | |||
The explained differences are all the same two behaviours of objdump:
- For an encoding that is not an instruction, the ESP32 and ESP32-S3 builds print the first opcode of their table,
lsi, with the fields they find; the ESP32-S2 build prints a one-byte.byte. The explorer keeps the length the opcode gives (3 or 2 bytes) so the instructions that follow line up as the hardware reads them. - Objdump decodes only the bits that tell its opcodes apart, so it reads
ret,retw,ret.nandretw.nwhatever theirsfield holds (60 words in each run). The explorer calls a nonzerosreserved.
On the ESP32-S3, 190 of the 217 EE.* mnemonics are decoded. A random sample of 80,000 32-bit words showed no difference from objdump in the decoded ones; the 27 missing mnemonics are rare 32-bit forms whose encodings did not turn up. Not every word of the 32-bit space was compared (it has 229 words).
Not described
Known, not yet covered
- Reference and viewer: the generic Xtensa configuration's cache, prefetch and MMU-register instructions, and the FLIX bundles of its objdump; no ESP chip has them.
- Viewer: the ESP8266 has no independent decoder to compare with here beyond the configuration file.
Unknown
- Reference: whether the ESP32-S2 lacks S32C1I and the loop option is established by objdump's behaviour; the S2 core file was not on this machine.
Links
Reference
- Espressif crosstool-NG – the toolchain whose objdump was the check
- Espressif QEMU – the emulator whose core configuration files list each core's options