ESP32-S3 Vector (PIE) Instructions

Introduction

The ESP32-S3 adds a vector unit that Espressif calls PIE (processor instruction extensions). It has eight 128-bit registers q0 to q7, a 160-bit accumulator pair QACC (low and high halves), a 40-bit accumulator ACCX, an unaligned-load state UA_STATE, a byte shift amount SAR_BYTE and an FFT width register, all reached as user registers. The instructions are used by Espressif's neural-network and DSP libraries (esp-nn, esp-dsp); the real firmware on this machine contains tens of thousands of them.

They come in two sizes. Many are 24-bit (op0 4, plus two at op0 0); the ones that do two things at once (a multiply and a load, with a pointer update) are 32-bit, op0 14 or 15, where the low bit of op0 is part of a register field. Operand fields are scattered over the word, so the explorer's table records each operand as a list of bit positions; the vector registers' three bits are not adjacent.

Suffixes: .ip adds an immediate to the address register afterwards, .xp adds a register, .incp increments by the access size, .decp decrements, .qup also moves the unaligned-load state, .ld and .st add a load or a store. The element types are s8, s16, s32, u8, u16.

This is what the Espressif objdump decodes, 190 of the 217 mnemonics of its ESP32-S3 configuration. The remaining 27 (rare 32-bit forms) are not in the explorer's decoder; they show as reserved encodings. The descriptions below are from the instruction names and the operand shapes, not from Espressif's manual, which was not read.

Vector loads and stores

Accumulator loads and stores, moves

Logic, shifts and rearrangement

Lane arithmetic

Multiply-accumulate

The .accx forms add the sum of the lane products to ACCX; the .qacc forms accumulate each lane into QACC. The 32-bit forms do the multiply and a load in one instruction.

Lane arithmetic fused with a load or a store (32-bit)

FFT and floating-point helpers

GPIO

Not described

Known, not yet covered

• Reference and viewer: 27 of the 217 mnemonics of the S3 configuration, all rare 32-bit forms: they decode as reserved encodings.
• Reference: what each instruction computes exactly (saturation, rounding, the meaning of the selector operands, the state in UA_STATE and SAR_BYTE).

Unknown

• Reference: Espressif's own description of these instructions was not read; the one-line descriptions come from the mnemonics and the operand shapes, and are hedged accordingly.

Links