Xtensa Options

Introduction

Each option is in some cores and not in others; the chips page says which chip has which. The explorer shows an instruction of an option the chosen chip lacks as unavailable.

Code Density: 16-bit instructions

The first byte's op0 of 8 to 13 makes a 2-byte instruction. The fields are r s t op0 (nibbles from the top). Every ESP chip has them.

Instruction	Encoding	What it does
`l32i.n at, as, 0..60`	`i s t 8`	Load a word; the offset is `i` times 4.
`s32i.n at, as, 0..60`	`i s t 9`	Store a word.
`add.n ar, as, at`	`r s t a`	ar = as + at.
`addi.n ar, as, imm`	`r s t b`	Add -1 or 1 to 15: the field `t` is the immediate, with 0 meaning -1.
`movi.n as, imm`	`i s 0j c`	Load -32 to 95: the 7-bit field is `j:i` (`j` is 3 bits of `t`); 96 to 127 are -32 to -1.
`beqz.n as, target`	`i s 10j c`	Branch forward 0 to 63 bytes (from pc + 4) if as is zero; the 6-bit offset is `j:i`.
`bnez.n as, target`	`i s 11j c`	Branch forward if as is not zero.
`mov.n at, as`	`0 s t d`	Move.
`ret.n`	`f 0 0 d`	Return, 2 bytes.
`break.n n`	`f s 2 d`	Breakpoint, 2 bytes; `s` is the immediate.
`nop.n`	`f 0 3 d`	No operation, 2 bytes.
`ill.n`	`f 0 6 d`	Illegal instruction, 2 bytes.

RETW.N is on the windowed registers page. The other narrow values of op0 (op0 12 with other t patterns, 13 with other r fields) are not instructions.

Zero-overhead loops

LOOP as, end sets LCOUNT to as minus 1, LBEG to the next instruction and LEND to the end label (pc + 4 + imm8, unsigned), and the processor then jumps back from LEND to LBEG without an instruction until LCOUNT runs out. Not on the ESP32-S2 or ESP8266.

Instruction	Encoding	What it does
`loop as, end`	`i i 8 s 7 6`	Repeat the loop body as times (at least once).
`loopnez as, end`	`i i 9 s 7 6`	Skip the body (jump to the end label) if as is zero.
`loopgtz as, end`	`i i a s 7 6`	Skip the body if as is zero or negative.

Boolean registers

Sixteen one-bit registers b0 to b15, held as the special register BR; the floating-point compares write them. Not on the ESP32-S2 or ESP8266.

Instruction	Encoding	What it does
`bf bs, target`	`i i 0 s 7 6`	Branch if boolean bs is false.
`bt bs, target`	`i i 1 s 7 6`	Branch if boolean bs is true.
`andb br, bs, bt`	`0 2 r s t 0`	Boolean AND.
`andbc br, bs, bt`	`1 2 r s t 0`	bs AND NOT bt.
`orb br, bs, bt`	`2 2 r s t 0`	Boolean OR.
`orbc br, bs, bt`	`3 2 r s t 0`	bs OR NOT bt.
`xorb br, bs, bt`	`4 2 r s t 0`	Boolean exclusive OR.
`any4 bt, bs:bs+3`	`0 0 8 s t 0`	bt = any of four consecutive booleans is true; the group starts at a multiple of 4 (the low bits of `s` are ignored).
`all4 bt, bs:bs+3`	`0 0 9 s t 0`	bt = all four are true.
`any8 bt, bs:bs+7`	`0 0 a s t 0`	bt = any of eight is true; the group starts at 0 or 8.
`all8 bt, bs:bs+7`	`0 0 b s t 0`	bt = all eight are true.
`movf ar, as, bt`	`c 3 r s t 0`	ar = as if boolean bt is false.
`movt ar, as, bt`	`d 3 r s t 0`	ar = as if boolean bt is true.

Multiply and divide

Instruction	Encoding	What it does
`mull ar, as, at`	`8 2 r s t 0`	The low 32 bits of as times at (MUL32; all four chips).
`muluh ar, as, at`	`a 2 r s t 0`	The high 32 bits, unsigned (MUL32 HIGH; not the ESP8266).
`mulsh ar, as, at`	`b 2 r s t 0`	The high 32 bits, signed.
`quou ar, as, at`	`c 2 r s t 0`	Unsigned divide: the quotient (DIV32; not the ESP8266). Division by zero raises an exception.
`quos ar, as, at`	`d 2 r s t 0`	Signed divide: the quotient.
`remu ar, as, at`	`e 2 r s t 0`	Unsigned remainder.
`rems ar, as, at`	`f 2 r s t 0`	Signed remainder.
`mul16u ar, as, at`	`c 1 r s t 0`	The low 16 bits of as times the low 16 bits of at, unsigned.
`mul16s ar, as, at`	`d 1 r s t 0`	The same, signed.

MAC16: 16-bit multiply-accumulate

A 40-bit accumulator ACC (the special registers ACCLO and ACCHI) and four 32-bit registers m0 to m3 (M0 to M3). The multiplies take a 16-bit half from each operand: the suffix is the half of the first operand and then of the second (ll low-low, hl, lh, hh). The operand types: aa two address registers; ad an address register and m2/m3; da m0/m1 and an address register; dd m0/m1 and m2/m3. The encoding is op2 op1 r s t 4. ESP32 and ESP32-S3 only.

Instruction	Encoding	What it does
`umul.aa.ll/hl/lh/hh as, at`	`7 0..3 0 s t 4`	Unsigned 16x16 multiply into ACC.
`mul.aa.xx as, at`	`7 4..7 0 s t 4`	Signed 16x16 multiply into ACC.
`mula.aa.xx as, at`	`7 8..b 0 s t 4`	Multiply and add to ACC.
`muls.aa.xx as, at`	`7 c..f 0 s t 4`	Multiply and subtract from ACC.
`mul.ad.xx as, my`	`3 4..7 0 s 0y00 4`	Signed multiply of as and m2 or m3 (`y` chooses) into ACC.
`mula.ad.xx as, my`	`3 8..b 0 s 0y00 4`	Multiply and add.
`muls.ad.xx as, my`	`3 c..f 0 s 0y00 4`	Multiply and subtract.
`mul.da.xx mx, at`	`6 4..7 0x00 0 t 4`	Signed multiply of m0 or m1 (`x` chooses) and at.
`mula.da.xx mx, at`	`6 8..b 0x00 0 t 4`	Multiply and add.
`muls.da.xx mx, at`	`6 c..f 0x00 0 t 4`	Multiply and subtract.
`mul.dd.xx mx, my`	`2 4..7 0x00 0 0y00 4`	Signed multiply of two m registers.
`mula.dd.xx mx, my`	`2 8..b 0x00 0 0y00 4`	Multiply and add.
`muls.dd.xx mx, my`	`2 c..f 0x00 0 0y00 4`	Multiply and subtract.
`mula.da.xx.ldinc mw, as, mx, at`	`4 8..b 0xww s t 4`	Multiply-accumulate and load m[w] from [as], then as += 4.
`mula.da.xx.lddec mw, as, mx, at`	`5 8..b 0xww s t 4`	The same, then as -= 4.
`mula.dd.xx.ldinc mw, as, mx, my`	`0 8..b 0xww s 0y00 4`	Multiply-accumulate and load, then as += 4.
`mula.dd.xx.lddec mw, as, mx, my`	`1 8..b 0xww s 0y00 4`	The same, then as -= 4.
`ldinc mw, as`	`8 0 00ww s 0 4`	Load m[w] from [as], then as += 4.
`lddec mw, as`	`9 0 00ww s 0 4`	Load m[w] from [as], then as -= 4.

Not described

Known, not yet covered

Reference: the exact saturation and rounding of the MAC16 results.
Reference: the options the ESP chips do not have (DEPBITS, DSP engines, the 64-bit FLIX bundles).

Unknown

Reference: the semantics are from the ISA manual as remembered; objdump confirms encodings, operand order and which bits it ignores.