Introduction
An Xtensa instruction is a little-endian word of 16, 24 or (ESP32-S3) 32 bits. Its length comes from op0, the low four bits of
the first byte. Fields are named by their place: in a 24-bit word, op0 is bits 3 to 0, t bits 7 to 4, s bits
11 to 8, r bits 15 to 12, op1 bits 19 to 16 and op2 bits 23 to 20. Immediates use the same bits
(imm8 is bits 23 to 16, imm16 bits 23 to 8, imm12 bits 23 to 12, the 18-bit call offset bits 23 to 6).
A big-endian core stores the fields in the opposite order (op0 in the top nibble of the first byte).
Instruction length
op0 | Length | Meaning |
|---|---|---|
| 0 to 7 | 3 bytes | The 24-bit formats. |
| 8 to 13 | 2 bytes | Code Density (16-bit) instructions. |
| 14, 15 | 4 bytes on the ESP32-S3; elsewhere reserved | The 32-bit vector format. On the other ESP chips objdump prints a 1-byte .byte for a reserved op0; the explorer shows a one-byte reserved item. |
The 24-bit formats
| Format | Fields | Used by |
|---|---|---|
| RRR | op2 op1 r s t op0 | Arithmetic, shifts, the FPU, the system group. |
| RRI8 | imm8 r s t op0 | Loads and stores, addi, the two-register branches (r chooses the operation). |
| RI16 | imm16 t op0 | l32r. |
| RSR | op2 op1 sr t op0 | rsr, wsr, xsr (the register number is r:s). |
| CALL | offset18 n op0 | call0, call4, call8, call12, j. |
| CALLX | op2 op1 r s m n op0 | callx0 to callx12, jx, ret. |
| BRI8 | imm8 r s m n op0 | beqi, bnei, blti, bgei, bltui, bgeui, bf, bt, loop. |
| BRI12 | imm12 s m n op0 | beqz, bnez, bltz, bgez, entry. |
The explorer's instruction table writes each encoding as six groups (op2 op1 r s t op0) with a letter for each field, and the
instruction pages repeat it.
The op0 decode tree
op0 | Group | What is there |
|---|---|---|
| 0 | QRST | All the register-register instructions, selected by op1 and op2. op1 0: add, subtract, logic, neg/abs, and (by op2 0) the system, synchronisation and call/return group, (4) the shift-amount, nsa and rer group, (5) the TLB group. 1: shifts, mul16, xsr. 2: booleans, multiply, divide. 3: rsr, wsr, rur, wur, min/max, clamps, sext, conditional moves. 4 and 5: extui. 8: the FPU indexed loads and stores. 9: l32e, s32e, s32nb. a: FPU arithmetic. b: FPU compares and conditional moves. e and f: the Espressif additions and the user-register moves. |
| 1 | L32R | l32r. |
| 2 | LSAI | Loads, stores, movi, addi, addmi, s32c1i; r chooses. |
| 3 | LSCI | The FPU loads and stores (lsi, ssi, lsip, ssip); bits 15 and 14 choose. |
| 4 | MAC16 | The MAC16 instructions; on the ESP32-S3 also most 24-bit vector instructions. |
| 5 | CALLN | The four calls, n (bits 5 and 4) chooses. |
| 6 | SI | j, the compare-with-zero branches, beqi and the other constant branches, entry, bf, bt, loop. |
| 7 | B | The two-register branches; r chooses. |
| 8 | L32I.N | l32i.n. |
| 9 | S32I.N | s32i.n. |
| 10 | ADD.N | add.n. |
| 11 | ADDI.N | addi.n. |
| 12 | ST2 | movi.n, beqz.n, bnez.n (bits 7 and 6 choose). |
| 13 | ST3 | mov.n, and with r = 15 ret.n, retw.n, break.n, nop.n, ill.n. |
| 14, 15 | vector | ESP32-S3 only: 32-bit vector instructions. |
A word that matches no instruction is not decoded. Objdump decodes only the bits that tell its instructions apart, so it accepts
some words whose other fixed bits are not zero (for example ret with a nonzero s); the explorer calls those reserved.
The 32-bit vector format (ESP32-S3)
Bits 3 to 0 are 111x; the lowest bit is not a format bit but part of an operand field (the third bit of a vector register
number). The fields are scattered: the vector page lists the instructions.
Not described
Known, not yet covered
- Reference: the FLIX 64-bit bundles of Xtensa configurations that define them; no ESP chip does.
Unknown
- Reference: the format names (RRR, RRI8 and the others) are from the ISA manual as remembered.
Links
Reference
- Tensilica – the Xtensa architecture