Xtensa Espressif Additions

Introduction

Xtensa lets a licensee add instructions. Espressif added some to each chip. They are not in Tensilica's documentation, so this page gives the encodings and operands as the Espressif toolchain's objdump decodes them, and says nothing about what the instructions compute beyond their names. Which chip has which is on the chips page.

F64: double-precision helpers (ESP32)

The ESP32's FPU is single-precision. The compiler's double-precision software routines use these instructions, with the user registers F64R_LO, F64R_HI and F64S. The immediates are small fields (j, k) of the encoding.

Instruction	Encoding	Operands
`f64addc at, as, j, k`	`f b 0jjk s t 0`	Two address registers and two small immediates (`j` 2 bits, `k` 1 bit).
`f64subc at, as, j, k`	`f b 1jjk s t 0`	The same shape.
`f64cmph ar, as, at, m`	`m f r s t 0`	Three address registers and a 4-bit immediate.
`f64cmpl ar, as, at`	`e b r s t 0`	Three address registers.
`f64iter ar, as, at, j, k`	`1kjj e r s t 0`	Three registers and two immediates (2 and 1 bits).
`f64rnd ar, as, at, j`	`01jj e r s t 0`	Three registers and a 2-bit immediate.
`f64norm ar, as, at, j`	`001j e r s t 0`	Three registers and a 1-bit immediate.
`f64sexp ar, as, at`	`0001 e r s t 0`	Three address registers.
`f64sig at, as`	`0 e d s t 0`	Two address registers.
`wf64r as, at, j`	`0 b 111j s t 0`	Two address registers and a 1-bit immediate.
`rf64r at, j`	`0 b c 111j t 0`	An address register and a 1-bit immediate.

EXPSTATE: GPIO export state (ESP32)

Instruction	Encoding	Operands
`read_impwire at`	`0 e 0 0 t 0`	Reads the IMPWIRE input wires into at.
`setb_expstate n`	`0 e 1 000j j 0`	Sets bit n (0 to 31) of EXPSTATE.
`clrb_expstate n`	`0 e 1 001j j 0`	Clears bit n of EXPSTATE.
`wrmsk_expstate at, as`	`0 e 2 s t 0`	Writes EXPSTATE through a mask (the registers hold the value and the mask).

ESP32-S2 and ESP32-S3: SALT, GPIO

Instruction	Encoding	What it does
`salt ar, as, at`	`7 2 r s t 0`	Set ar to 1 if as is less than at (signed), else 0. ESP32-S2 and ESP32-S3.
`saltu ar, as, at`	`6 2 r s t 0`	The same, unsigned.
`clr_bit_gpio_out n`	`0 6 0 s t 0`	Clear bit n (an 8-bit immediate, `s:t`) of the GPIO output register. ESP32-S2 only; the S3 has `ee.clr_bit_gpio_out`.
`set_bit_gpio_out n`	`0 6 1 s t 0`	Set a bit of the GPIO output register. ESP32-S2 only.
`wr_mask_gpio_out as, at`	`0 6 2 s t 0`	Write the GPIO output register under a mask: value in as, mask in at (as the names say). ESP32-S2 only.
`get_gpio_in at`	`0 6 3 0 t 0`	Read the GPIO input pins into at. ESP32-S2 only.

S32NB

Instruction	Encoding	What it does
`s32nb at, as, 0..60`	`5 9 r s t 0`	Store a word, the offset being `r` times 4; the name suggests a store without write buffering (ESP32, ESP32-S2 and ESP32-S3).

Not described

Known, not yet covered

Reference: what the F64 instructions compute, how the compiler uses them, and the EXPSTATE and IMPWIRE pins.

Unknown

Reference: Espressif has not published these instructions as far as was found; the operand roles (which register is written) are given from objdump's operand order and not otherwise checked.
Reference: the description of s32nb is inferred from its name.