What each instruction set adds
| Set | Adds to the one before |
|---|---|
| MIPS I | The base: the integer instructions, loads and stores with the load delay slot, branches with a delay slot, mult and div with HI and LO, coprocessor 0 (the TLB and rfe), coprocessors 1 to 3. |
| MIPS II | Branch likely, ll and sc, sync, the traps, sqrt and the rounding conversions to a word, ldc1 and sdc1, load interlocks (no load delay slot). |
| MIPS III | The 64-bit registers: the d-instructions (daddu, dsll, dmult …), ld, sd, lwu, ldl/ldr, lld/scd, eret, cache, the conversions to and from a long, 64-bit coprocessor moves. |
| MIPS IV | movz, movn, movf, movt and the floating-point forms, pref, the eight floating-point condition codes, COP1X (indexed loads and stores, multiply-add, recip, rsqrt). |
| MIPS V | Paired single. |
| MIPS32 and MIPS64 Release 1 | MIPS II plus mul, madd, msub, clz, clo, sdbbp, wait, the select field of coprocessor 0 moves; with the MIPS IV conditional moves, pref, cache. MIPS64 adds the 64-bit instructions and dclz, dclo. |
| Release 2 | ext, ins, rotr, wsbh, seb, seh, rdhwr, di, ei, synci, jr.hb, mfhc1, mthc1, the shadow registers, and for 64-bit dext, dins, dsbh, dshd, drotr. |
| Release 5 | tlbinv, tlbinvf (the virtualisation and SIMD modules are not decoded). |
| Release 6 | See Release 6: a different instruction set that is no longer a superset. |
A word of a later set shown with an earlier variant selected is marked not in this ISA with the name of the set that has it.
The PlayStation R3000A
The Sony PlayStation's CPU is an LSI Logic CW33300, an R3000A core. The variant PlayStation CPU is MIPS I with these differences from a generic MIPS I:
- Little-endian: a PS-X EXE's words are stored low byte first; the variant's default byte order is little.
- No TLB:
tlbr,tlbwi,tlbwrandtlbpare not instructions of the PlayStation; the viewer shows them as not in this ISA. Coprocessor 0 has the debug and breakpoint registers in their place. - No floating-point unit: the COP1 opcodes and
lwc1,swc1are not instructions. - Coprocessor 2 is the GTE: 22 commands, the register moves, and
lwc2,swc2that load and store its registers. The commands are not valid in a generic MIPS I. - Uses the load delay slot.
rfereturns from exceptions. - The mnemonics were also checked against the PlayStation CPU disassembler of the emulators in this site (200,365 words named, none with a different mnemonic).
What the decoder does not claim: that the R3000A rejects every instruction of later sets in exactly the way it is shown (an unimplemented opcode raises a reserved instruction exception on the real chip, which is what “not in this ISA” stands for).
The Nintendo 64 VR4300
The NEC VR4300 is a MIPS III processor with a floating-point unit. The variant NEC VR4300 is MIPS III with: big-endian byte order by default; no coprocessor 2 (its opcodes are shown as not in this ISA); none of the MIPS IV additions (no movn, pref or indexed loads);
the 64-bit instructions, ll, sc, lld, scd, cache and the branch-likely forms; the TLB; eret.
The N64's second processor, the RSP (a signal processor that shares the MIPS integer set and adds a vector unit in coprocessor 2), is a different decoder that is not built.
- The mnemonics were checked against the VR4300 disassembler of the emulators in this site (404,073 words named, none with a different mnemonic).
- Not read: NEC's VR4300 user's manual. The variant follows MIPS III, and the pages say so where a VR4300 detail is not known.
Byte order
MIPS chips are bi-endian: the same instruction word is stored most significant byte first (big-endian: the Nintendo 64, most routers and workstations of the
1990s) or least significant first (little-endian: the PlayStation, many embedded boards). The decoder takes the byte order as an option. An ELF file says which it is;
a headerless file needs the choice, and the viewer does not guess. The words 27 bd ff e0 (big-endian) and e0 ff bd 27 (little-endian) are
the same instruction, addiu $sp, $sp, -32. A Nintendo 64 ROM can also be byte-swapped as a file (.v64, .n64); that is a
property of the file format, not of the CPU.
Where the decoder and llvm differ
The decoder is compared word by word with llvm-mc --disassemble for MIPS I, II, III, IV, V, MIPS32 Release 1, 2, 3, 5, 6 and MIPS64 Release 1, 2, 3, 5, 6 (llvm's own configuration names; Release 3 is compared with Release 2). Where they disagree, the decoder follows the architecture manuals and
the difference is recorded. The known differences:
| What | Why |
|---|---|
Paired single (*.ps, alnv.ps, cvt.ps.s, cvt.s.pl and pu…) | llvm has no paired-single instructions. |
wait, prefx, rfe, bc0f and bc2f families, cfc2, ctc2, tlbinv, tlbinvf | llvm does not decode them (or only in a few configurations). |
rdhwr | llvm decodes only hardware register 29. |
cmp.or, cmp.une, cmp.ne, cmp.sor, cmp.sune, cmp.sne (Release 6) | llvm has no such compare conditions. |
clz, clo, dclz, dclo with rt different from rd | The manual says rt must equal rd; llvm names rt as the destination. The explorer marks the word unpredictable. |
The condition-code field of bc1f, bc1t, c.cond in MIPS I to III | llvm decodes it in every configuration; MIPS I to III have no such field, so it is shown as unpredictable. |
pref in MIPS III, wait in MIPS IV and MIPS64, JR.HB and JALR.HB in MIPS32 and MIPS64 Release 1, scd and some 64-bit instructions in mips32r6, the L-format conversions in MIPS32 Release 1 | llvm accepts instructions of a later release in these configurations. The decoder shows them as not in this ISA, or as a different mnemonic. |
COP2 mfc2 etc. in MIPS I | llvm writes the MIPS32 select field in every configuration; the PlayStation form has none, and the decoder omits it for the PlayStation and VR4300 variants. |
Doubles in odd registers, and 64-bit-FPU instructions with fp64 off | llvm rejects them without the fp64 attribute; the decoder accepts them, and the comparison runs with fp64 on. |
teq in MIPS I (clang emits it for a division check) | TEQ is a MIPS II instruction; the decoder shows it as not in this ISA for MIPS I and the PlayStation. |
Names: lapc for addiupc, three-register div $zero, a, b, the unsigned 16-bit offset of jic and jialc, the doubled register and unsigned immediate of dahi and dati | llvm spellings; the comparison reduces both sides to one form. |
Not described
Known, not yet covered
- Reference and viewer: the instruction sets of the other MIPS-derived chips: PlayStation 2 R5900, PlayStation Portable Allegrex (its VFPU), the N64 RSP, Loongson, Octeon.
Unknown
- Reference: which instructions of a later set a particular shipped chip also decodes (chips are often more permissive than the architecture).