Introduction
Release 6 (2014) is not backward compatible with Releases 1 to 5: it removes instructions, reuses their opcodes for new ones and re-encodes others, which is why an R6 program is not a MIPS32 Release 2 program. The explorer's MIPS32 Release 6 and MIPS64 Release 6 variants decode it. A word that is an instruction of an earlier release but not of R6 is shown as not in this ISA, and the reverse. This page lists the changes; the instructions are on the group pages, marked “Release 6”.
Removed
| Removed | Replaced by |
|---|---|
Branch likely (beql, bnel, blezl, bgtzl, bltzl, bgezl, the …all forms and the coprocessor ones) | Nothing: use a normal branch or a compact branch. |
addi, daddi | addiu, daddiu (the opcodes became compact branches). |
HI and LO: mfhi, mthi, mflo, mtlo, madd, maddu, msub, msubu and the two-operand mult, div forms | mul, muh, mulu, muhu, div, mod, divu, modu (and the d-forms), three-register. |
movz, movn, movf, movt and the floating-point conditional moves | seleqz, selnez, sel.fmt, seleqz.fmt, selnez.fmt. |
The unaligned lwl, lwr, swl, swr, ldl, ldr, sdl, sdr | Hardware (or software-trapped) unaligned access; align, dalign for the bit work. |
The immediate traps tgei, tgeiu, tlti, tltiu, teqi, tnei | The register traps stay. |
The old ll, sc, lld, scd, cache, pref encodings; SPECIAL2 (clz and clo move) | The SPECIAL3 forms with a nine-bit offset; clz and clo in SPECIAL. |
c.cond.fmt, bc1f, bc1t and the eight condition codes | cmp.cond.fmt (a result in a floating-point register) with bc1eqz, bc1nez. |
COP1X: the indexed loads and stores, madd.fmt and the others, prefx, alnv.ps, and the whole paired-single set | Fused maddf.fmt, msubf.fmt; indexing through lsa. |
jalx, lui as an opcode of its own, the coprocessor 0 and coprocessor 2 branches | aui (lui is aui rt, $0, imm), daui; bc2eqz, bc2nez. |
Which compact branch a word is
Release 6 reuses four opcodes for several branches and tells them apart by comparing the register fields. This is what makes R6 branch decoding different:
| Opcode (bits 31–26) | Condition on rs, rt | Instruction |
|---|---|---|
6 (000110) | rt = 0 | blez rs (with a delay slot) |
| rs = 0, rt ≠ 0 | blezalc rt | |
| rs = rt ≠ 0 | bgezalc rt | |
| rs ≠ rt, both ≠ 0 | bgeuc rs, rt | |
7 (000111) | rt = 0 | bgtz rs |
| rs = 0, rt ≠ 0 | bgtzalc rt | |
| rs = rt ≠ 0 | bltzalc rt | |
| rs ≠ rt, both ≠ 0 | bltuc rs, rt | |
8 (001000) | rs = 0, rt ≠ 0 | beqzalc rt |
| 0 < rs < rt | beqc rs, rt | |
| rs ≥ rt | bovc rs, rt | |
24 (011000) | rs = 0, rt ≠ 0 | bnezalc rt |
| 0 < rs < rt | bnec rs, rt | |
| rs ≥ rt | bnvc rs, rt | |
22 (010110) | rs = 0, rt ≠ 0 | blezc rt |
| rs = rt ≠ 0 | bgezc rt | |
| rs ≠ rt, both ≠ 0 | bgec rs, rt | |
23 (010111) | rs = 0, rt ≠ 0 | bgtzc rt |
| rs = rt ≠ 0 | bltzc rt | |
| rs ≠ rt, both ≠ 0 | bltc rs, rt | |
54 (110110) | rs = 0 | jic rt, offset |
| rs ≠ 0 | beqzc rs, offset21 | |
62 (111110) | rs = 0 | jialc rt, offset |
| rs ≠ 0 | bnezc rs, offset21 |
The words that fit no row (for example opcode 22 with rt = 0) are reserved. The decision rules were checked against llvm for every pair of registers.
Added
- Multiply and divide into a register: mul, muh, mulu, muhu, div, mod, divu, modu and the 64-bit forms.
- lsa and dlsa (scaled add), bitswap, align and the 64-bit forms,
clzandclo. - seleqz and selnez; the floating-point select, min, max, class, rint, fused multiply-add and cmp.
- PC-relative: addiupc, auipc, aluipc and the loads lwpc, lwupc, ldpc.
- The upper-immediate family aui, daui, dahi, dati, which build 32-, 48- and 64-bit constants.
- The compact branches and jumps with no delay slot, and
nal,bal,sigrie. - The coprocessor 2 loads and stores re-encoded in COP2 (
lwc2,swc2,ldc2,sdc2) with an 11-bit offset, andbc2eqz,bc2nez. dvpandevp.
Not described
Known, not yet covered
- Reference: the Release 6 privileged-architecture changes (the TLB and exception behaviour), the CRC and GINV instructions, the MSA and virtualisation modules.
Unknown
- Reference: the exact trapping of every reserved R6 encoding (the manual says which are reserved, not what each does).