The three formats
Every instruction is one 32-bit word, written most significant bit first here. In memory its bytes are in the machine's byte order: big-endian on the Nintendo 64 and in most embedded and network chips, little-endian on the PlayStation.
| Format | 31–26 | 25–21 | 20–16 | 15–11 | 10–6 | 5–0 |
|---|---|---|---|---|---|---|
| R (register) | opcode | rs | rt | rd | sa (shift amount) | function |
| I (immediate) | opcode | rs | rt | 16-bit immediate or branch offset | ||
| J (jump) | opcode | 26-bit target | ||||
Fields: rs and rt are source registers (and rt the destination of an I-type);
rd the destination of an R-type; sa a shift amount. A coprocessor instruction has its own layout under
opcodes 16 to 19; for floating point, fmt (bits 25–21) says single, double, word or long, ft (20–16),
fs (15–11) and fd (10–6) name floating-point registers.
A branch offset is a signed 16-bit count of instructions, counted from the instruction after the branch (the
delay slot): the target is delay slot address + offset × 4, so it reaches 128 KB back and 128 KB − 4 forward. Release 6 compact branches have longer offsets
(21 and 26 bits). A jump takes the top four bits of the delay slot's address and the 26-bit target times four:
it stays within the current 256 MB region. jr and jalr jump anywhere.
The primary opcode map (bits 31–26)
A dash marks an encoding that no instruction set before Release 6 uses; a name in parentheses is what Release 6 does with the opcode.
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | |
|---|---|---|---|---|---|---|---|---|
| 0 | SPECIAL | REGIMM | j | jal | beq | bne | blez | bgtz |
| 1 | addi (beqzalc, beqc, bovc) | addiu | slti | sltiu | andi | ori | xori | lui (aui) |
| 2 | COP0 | COP1 | COP2 | COP1X | beql | bnel | blezl | bgtzl |
| 3 | daddi (bnezalc, bnec, bnvc) | daddiu | ldl | ldr | SPECIAL2 | jalx (daui) | MSA (reserved) | SPECIAL3 |
| 4 | lb | lh | lwl | lw | lbu | lhu | lwr | lwu |
| 5 | sb | sh | swl | sw | sdl | sdr | swr | cache |
| 6 | ll | lwc1 | lwc2 (bc) | pref (lwc3 on MIPS I and II) | lld | ldc1 | ldc2 (jic, beqzc) | ld (ldc3 on MIPS II) |
| 7 | sc | swc1 | swc2 (balc) | PCREL (swc3 on MIPS I and II) | scd | sdc1 | sdc2 (jialc, bnezc) | sd (sdc3 on MIPS II) |
Row n, column m is opcode 8 × n + m. Release 6 also shares opcodes between instructions told apart by their register
fields: opcodes 6 and 7 hold BLEZ and BGTZ with the compact branch-and-link forms, opcodes 8 and 24 hold the compact equal and
not-equal branches, and opcodes 22 and 23 (the old BLEZL and BGTZL) hold BLEZC, BGEZC, BGEC and BGTZC, BLTZC, BLTC. See
Release 6.
SPECIAL (opcode 0), selected by bits 5–0
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | |
|---|---|---|---|---|---|---|---|---|
| 0 | sll | movci | srl, rotr | sra | sllv | (lsa) | srlv, rotrv | srav |
| 1 | jr | jalr | movz | movn | syscall | break | sdbbp (R6) | sync |
| 2 | mfhi (clz) | mthi (clo) | mflo (dclz) | mtlo (dclo) | dsllv | (dlsa) | dsrlv, drotrv | dsrav |
| 3 | mult (mul, muh) | multu (mulu, muhu) | div (div, mod) | divu (divu, modu) | dmult | dmultu | ddiv | ddivu |
| 4 | add | addu | sub | subu | and | or | xor | nor |
| 5 | – | – | slt | sltu | dadd | daddu | dsub | dsubu |
| 6 | tge | tgeu | tlt | tltu | teq | (seleqz) | tne | (selnez) |
| 7 | dsll | – | dsrl, drotr | dsra | dsll32 | – | dsrl32, drotr32 | dsra32 |
In the table SPECIAL row n is function 8 × n + column (so movz is 10 and seleqz is 53). The SPECIAL2 opcode (28) holds madd, maddu,
mul, msub, msubu, clz, clo, dclz, dclo and sdbbp, up to MIPS32 and MIPS64 Release 5; Release 6 removes it. The SPECIAL3 opcode (31)
holds ext, ins, the byte and bit swaps, rdhwr, and in Release 6 the 9-bit-offset ll, sc, cache and pref.
REGIMM (opcode 1), selected by bits 20–16
The rt field picks the instruction: 0 bltz, 1 bgez, 2 bltzl, 3 bgezl, 8 to 14 the traps with an immediate (tgei,
tgeiu, tlti, tltiu, teqi, tnei), 16 bltzal, 17 bgezal, 18 bltzall, 19 bgezall, 31 synci. Release 6 uses 6 for dahi, 30 for dati,
16 and 17 with rs = 0 for nal and bal, and 23 for sigrie.
Coprocessor opcodes
COP0, COP1 and COP2 (opcodes 16, 17, 18) select the instruction by bits 25–21: 0 mfc, 1 dmfc, 2 cfc, 3 mfhc (Release 2), 4 mtc, 5 dmtc, 6 ctc, 7 mthc, 8 the branches, and from 16 up (bit 25 set) a coprocessor operation: for COP0 the function in bits 5–0 (tlbr, eret ...), for COP1 the format in bits 25–21 and the function in bits 5–0, for COP2 a command defined by the coprocessor (the GTE on the PlayStation). COP1X (opcode 19) holds the indexed floating-point loads and stores, the multiply-adds and PREFX.
Not described
Known, not yet covered
- Reference: the 16-bit encodings of MIPS16e and microMIPS, and the DSP, MSA, MT and VZ encodings in SPECIAL3 and opcode 30.
Unknown
- Reference: none known.