Introduction
Memory is only reached by loads and stores. The address is base + offset: a general register plus a signed 16-bit
offset (nine bits for the Release 6 forms). An access must be aligned to its size or it raises an address error, except the
unaligned left/right pairs below. Loads sign-extend (or zero-extend with a u) to the register width. On MIPS I a loaded
register is not usable by the next instruction: see the load delay slot.
Integer loads and stores
| Instruction | Encoding | ISA | What it does |
|---|---|---|---|
lb rt, offset(base) | 100000 base rt offset | MIPS I | Load a byte, sign-extended. |
lbu rt, offset(base) | 100100 base rt offset | MIPS I | Load a byte, zero-extended. |
lh rt, offset(base) | 100001 base rt offset | MIPS I | Load a halfword, sign-extended. |
lhu rt, offset(base) | 100101 base rt offset | MIPS I | Load a halfword, zero-extended. |
lw rt, offset(base) | 100011 base rt offset | MIPS I | Load a word, sign-extended to 64 bits on a 64-bit processor. |
lwu rt, offset(base) | 100111 base rt offset | MIPS III | Load a word, zero-extended. |
ld rt, offset(base) | 110111 base rt offset | MIPS III | Load a doubleword. |
sb rt, offset(base) | 101000 base rt offset | MIPS I | Store the low byte of rt. |
sh rt, offset(base) | 101001 base rt offset | MIPS I | Store the low halfword. |
sw rt, offset(base) | 101011 base rt offset | MIPS I | Store the low word. |
sd rt, offset(base) | 111111 base rt offset | MIPS III | Store a doubleword. |
Unaligned access: left and right
A word at an address that is not a multiple of four is loaded by a pair: lwl rt, offset(base) and lwr rt, offset+3(base)
(big-endian; the offsets swap on a little-endian machine). Each merges the bytes of one aligned word into rt and leaves the other bytes alone,
so the pair fills the register. They are removed in Release 6, which instead requires unaligned access to work (or traps for the OS to emulate it).
| Instruction | Encoding | ISA | What it does |
|---|---|---|---|
lwl rt, offset(base) | 100010 base rt offset | MIPS I (not R6) | Load the left part of an unaligned word: the bytes that go to the most significant end of the register (the lower addresses on a big-endian machine). |
lwr rt, offset(base) | 100110 base rt offset | MIPS I (not R6) | Load the right part. |
swl rt, offset(base) | 101010 base rt offset | MIPS I (not R6) | Store the left part of an unaligned word. |
swr rt, offset(base) | 101110 base rt offset | MIPS I (not R6) | Store the right part. |
ldl rt, offset(base) | 011010 base rt offset | MIPS III (not R6) | Load the left part of an unaligned doubleword. |
ldr rt, offset(base) | 011011 base rt offset | MIPS III (not R6) | Load the right part. |
sdl rt, offset(base) | 101100 base rt offset | MIPS III (not R6) | Store the left part of an unaligned doubleword. |
sdr rt, offset(base) | 101101 base rt offset | MIPS III (not R6) | Store the right part. |
Load linked and store conditional
A pair that makes an atomic read-modify-write: ll loads and starts watching the address, sc stores only if nothing
else has written the address since, and sets rt to 1 (stored) or 0 (failed). Both take the old register value of rt.
Release 6 re-encodes them with a nine-bit offset.
| Instruction | Encoding | ISA | What it does |
|---|---|---|---|
ll rt, offset(base) | 110000 base rt offset16 / R6 011111 base rt offset9 0 110110 | MIPS II / Release 6 | Load linked word. |
sc rt, offset(base) | 111000 base rt offset16 / R6 011111 base rt offset9 0 100110 | MIPS II / Release 6 | Store conditional word; rt receives the success flag. |
lld rt, offset(base) | 110100 base rt offset16 / R6 … 110111 | MIPS III / Release 6 | Load linked doubleword. |
scd rt, offset(base) | 111100 base rt offset16 / R6 … 100111 | MIPS III / Release 6 | Store conditional doubleword. |
Coprocessor loads and stores
| Instruction | Encoding | ISA | What it does |
|---|---|---|---|
lwc1 ft, offset(base) | 110001 base ft offset | MIPS I | Load a word into floating-point register ft. |
swc1 ft, offset(base) | 111001 base ft offset | MIPS I | Store a word from ft. |
ldc1 ft, offset(base) | 110101 base ft offset | MIPS II | Load a doubleword into ft (a register pair on a 32-bit FPU). |
sdc1 ft, offset(base) | 111101 base ft offset | MIPS II | Store a doubleword from ft. |
lwxc1 fd, index(base) | 010011 base index 0 fd 000000 | MIPS IV, MIPS32 Release 2 (not R6) | Load a word from base + index (both registers). |
ldxc1 fd, index(base) | 010011 base index 0 fd 000001 | MIPS IV, Release 2 (not R6) | Load a doubleword indexed. |
luxc1 fd, index(base) | 010011 base index 0 fd 000101 | MIPS V, Release 2 (not R6) | Load a doubleword indexed, ignoring the low three address bits. |
swxc1 fs, index(base) | 010011 base index fs 0 001000 | MIPS IV, Release 2 (not R6) | Store a word indexed. |
sdxc1 fs, index(base) | 010011 base index fs 0 001001 | MIPS IV, Release 2 (not R6) | Store a doubleword indexed. |
suxc1 fs, index(base) | 010011 base index fs 0 001101 | MIPS V, Release 2 (not R6) | Store a doubleword indexed, ignoring the low three address bits. |
lwc2 rt, offset(base) | 110010 base rt offset / R6 010010 01010 rt base offset11 | MIPS I / Release 6 | Load a word into coprocessor 2 register rt (on the PlayStation, a GTE data register). |
swc2 rt, offset(base) | 111010 base rt offset / R6 010010 01011 … | MIPS I / Release 6 | Store a word from coprocessor 2 register rt. |
ldc2 rt, offset(base) | 110110 base rt offset / R6 010010 01110 … | MIPS II / Release 6 | Load a doubleword into coprocessor 2. |
sdc2 rt, offset(base) | 111110 base rt offset / R6 010010 01111 … | MIPS II / Release 6 | Store a doubleword from coprocessor 2. |
lwc3 rt, offset(base) | 110011 base rt offset | MIPS I and II only | Load a word into coprocessor 3. MIPS IV reuses the opcode for pref. |
swc3 rt, offset(base) | 111011 base rt offset | MIPS I and II only | Store a word from coprocessor 3. |
ldc3 rt, offset(base) | 110111 base rt offset | MIPS II only | Load a doubleword into coprocessor 3. MIPS III makes the opcode ld. |
sdc3 rt, offset(base) | 111111 base rt offset | MIPS II only | Store a doubleword from coprocessor 3. MIPS III makes the opcode sd. |
PC-relative loads (Release 6)
| Instruction | Encoding | ISA | What it does |
|---|---|---|---|
lwpc rs, offset | 111011 rs 01 offset19 | Release 6 | Load the word at pc + (offset << 2). |
lwupc rs, offset | 111011 rs 10 offset19 | Release 6, 64-bit | The same, zero-extended. |
ldpc rs, offset | 111011 rs 110 offset18 | Release 6, 64-bit | Load the doubleword at the doubleword-aligned pc + (offset << 3). |
Not described
Known, not yet covered
- Reference: the EVA (enhanced virtual addressing) loads and stores, the DSP indexed loads (
lbux,lhx,lwx) and the MSA vector loads.
Unknown
- Reference: none known.