Introduction
Before Release 6 every jump and branch has a delay slot. The target of a branch is
(address of the delay slot) + offset × 4; of j and jal the top four bits of the delay
slot's address with the 26-bit target times four; of jr and jalr the register. The disassembly shows the target address
(with the “offset” setting, the byte offset from the delay slot, as llvm writes it), and in the explorer selecting a branch
offers to go to its target. The linking forms write the address of the delay slot plus four into $ra
(or into rd for jalr).
Jumps, calls and returns
| Instruction | Encoding | ISA | What it does |
|---|---|---|---|
j target | 000010 target26 | MIPS I | Jump within the 256 MB region of the delay slot. |
jal target | 000011 target26 | MIPS I | Call: $ra gets the return address, then jump. |
jalx target | 011101 target26 | MIPS32 (not R6) | Call and switch between the 32-bit and the MIPS16e or microMIPS instruction set. Release 6 gives the opcode to daui. |
jr rs | 000000 rs 0 hint 001000 | MIPS I | Jump to the address in rs. jr $ra is the function return. The explorer shows jr $ra as a return. |
jr.hb rs | 000000 rs 0 1 0000 001000 | Release 2 | Jump and clear execution hazards (the hb bit of the hint field). |
jalr rd, rs | 000000 rs 0 rd hint 001001 | MIPS I | Call a register: rd (default $ra) gets the return address. jalr $0, rs is jr; the Release 6 encoding of jr. |
jalr.hb rd, rs | 000000 rs 0 rd 1 0000 001001 | Release 2 | Call a register and clear execution hazards. |
Conditional branches
| Instruction | Encoding | ISA | Branches when |
|---|---|---|---|
beq rs, rt, offset | 000100 rs rt offset16 | MIPS I | rs equals rt. beq $0,$0 is the unconditional b; beq rs,$0 is beqz. |
bne rs, rt, offset | 000101 rs rt offset16 | MIPS I | rs differs from rt (bnez with $0). |
blez rs, offset | 000110 rs 0 offset16 | MIPS I | rs ≤ 0 (signed). |
bgtz rs, offset | 000111 rs 0 offset16 | MIPS I | rs > 0. |
bltz rs, offset | 000001 rs 00000 offset16 | MIPS I | rs < 0. |
bgez rs, offset | 000001 rs 00001 offset16 | MIPS I | rs ≥ 0. bgez $0 branches always. |
bltzal rs, offset | 000001 rs 10000 offset16 | MIPS I (not R6) | rs < 0, and writes the return address whether or not it branches. bltzal $0 is nal. |
bgezal rs, offset | 000001 rs 10001 offset16 | MIPS I (not R6) | rs ≥ 0, with the link. bgezal $0 is bal, a relative call. |
beql rs, rt, offset | 010100 rs rt offset16 | MIPS II (not R6) | Branch likely if equal. |
bnel rs, rt, offset | 010101 rs rt offset16 | MIPS II (not R6) | Branch likely if not equal. |
blezl rs, offset | 010110 rs 0 offset16 | MIPS II (not R6) | Branch likely if ≤ 0. |
bgtzl rs, offset | 010111 rs 0 offset16 | MIPS II (not R6) | Branch likely if > 0. |
bltzl rs, offset | 000001 rs 00010 offset16 | MIPS II (not R6) | Branch likely if < 0. |
bgezl rs, offset | 000001 rs 00011 offset16 | MIPS II (not R6) | Branch likely if ≥ 0. |
bltzall rs, offset | 000001 rs 10010 offset16 | MIPS II (not R6) | Branch and link likely if < 0. |
bgezall rs, offset | 000001 rs 10011 offset16 | MIPS II (not R6) | Branch and link likely if ≥ 0. |
Coprocessor branches
| Instruction | Encoding | ISA | Branches when |
|---|---|---|---|
bc1f [cc,] offset | 010001 01000 cc 0 0 offset16 | MIPS I (cc: MIPS IV) (not R6) | The floating-point condition flag (condition code cc) is false. |
bc1t [cc,] offset | 010001 01000 cc 0 1 offset16 | MIPS I (cc: MIPS IV) (not R6) | The condition flag is true. |
bc1fl [cc,] offset | 010001 01000 cc 1 0 offset16 | MIPS II (not R6) | Branch likely if false. |
bc1tl [cc,] offset | 010001 01000 cc 1 1 offset16 | MIPS II (not R6) | Branch likely if true. |
bc1eqz ft, offset | 010001 01001 ft offset16 | Release 6 | Bit 0 of floating-point register ft is zero (compact: no delay slot). |
bc1nez ft, offset | 010001 01101 ft offset16 | Release 6 | Bit 0 of ft is not zero. |
bc0f offset | 010000 01000 00000 offset16 | MIPS I (not R6) | The coprocessor 0 condition is false (what the condition signals is chip-specific; most chips define none). |
bc0t offset | 010000 01000 00001 offset16 | MIPS I (not R6) | The coprocessor 0 condition is true. |
bc0fl offset | 010000 01000 00010 offset16 | MIPS II (not R6) | Branch likely if false. |
bc0tl offset | 010000 01000 00011 offset16 | MIPS II (not R6) | Branch likely if true. |
bc2f offset | 010010 01000 00000 offset16 | MIPS I (not R6) | The coprocessor 2 condition is false (the PlayStation's GTE does not use it). |
bc2t offset | 010010 01000 00001 offset16 | MIPS I (not R6) | The coprocessor 2 condition is true. |
bc2fl offset | 010010 01000 00010 offset16 | MIPS II (not R6) | Branch likely if false. |
bc2tl offset | 010010 01000 00011 offset16 | MIPS II (not R6) | Branch likely if true. |
bc2eqz rt, offset | 010010 01001 rt offset16 | Release 6 | Bit 0 of coprocessor 2 register rt is zero. |
bc2nez rt, offset | 010010 01101 rt offset16 | Release 6 | Bit 0 of coprocessor 2 register rt is not zero. |
Release 6 compact branches and jumps
These have no delay slot: the next instruction is the forbidden slot. The same opcode holds several of them; the register fields choose
(for opcode 8: rs = 0 and rt ≠ 0 is beqzalc, rs < rt is beqc, otherwise bovc).
See Release 6 for the full decision table.
| Instruction | Encoding | Branches when |
|---|---|---|
bc offset | 110010 offset26 | Always (26-bit offset). |
balc offset | 111010 offset26 | Always, linking in $ra. |
beqzc rs, offset | 110110 rs offset21 (rs ≠ 0) | rs equals zero (21-bit offset). |
bnezc rs, offset | 111110 rs offset21 (rs ≠ 0) | rs differs from zero. |
jic rt, offset | 110110 00000 rt offset16 | Jump to rt + offset (jrc rt when the offset is 0). |
jialc rt, offset | 111110 00000 rt offset16 | Jump to rt + offset, linking in $ra. |
beqc rs, rt, offset | 001000 rs rt offset16 (0 < rs < rt) | rs equals rt. |
bnec rs, rt, offset | 011000 rs rt offset16 (0 < rs < rt) | rs differs from rt. |
bovc rs, rt, offset | 001000 rs rt offset16 (rs ≥ rt) | Adding rs and rt overflows 32 bits. |
bnvc rs, rt, offset | 011000 rs rt offset16 (rs ≥ rt) | Adding them does not overflow. |
beqzalc rt, offset | 001000 00000 rt offset16 (rt ≠ 0) | rt equals zero, linking. |
bnezalc rt, offset | 011000 00000 rt offset16 (rt ≠ 0) | rt differs from zero, linking. |
blezalc rt, offset | 000110 00000 rt offset16 (rt ≠ 0) | rt ≤ 0, linking. |
bgezalc rt, offset | 000110 rt rt offset16 (rt ≠ 0) | rt ≥ 0, linking. |
bgtzalc rt, offset | 000111 00000 rt offset16 (rt ≠ 0) | rt > 0, linking. |
bltzalc rt, offset | 000111 rt rt offset16 (rt ≠ 0) | rt < 0, linking. |
bgeuc rs, rt, offset | 000110 rs rt offset16 (rs ≠ rt, both ≠ 0) | rs ≥ rt, unsigned. |
bltuc rs, rt, offset | 000111 rs rt offset16 (rs ≠ rt, both ≠ 0) | rs < rt, unsigned. |
blezc rt, offset | 010110 00000 rt offset16 (rt ≠ 0) | rt ≤ 0. |
bgezc rt, offset | 010110 rt rt offset16 (rt ≠ 0) | rt ≥ 0. |
bgec rs, rt, offset | 010110 rs rt offset16 (rs ≠ rt, both ≠ 0) | rs ≥ rt, signed. |
bgtzc rt, offset | 010111 00000 rt offset16 (rt ≠ 0) | rt > 0. |
bltzc rt, offset | 010111 rt rt offset16 (rt ≠ 0) | rt < 0. |
bltc rs, rt, offset | 010111 rs rt offset16 (rs ≠ rt, both ≠ 0) | rs < rt, signed. |
Not described
Known, not yet covered
- Reference: the 16-bit jumps and branches of MIPS16e and microMIPS (
jrc,jalrc,bwith 11-bit offsets). - Viewer: following a jump through a register (
jr $t9after a table load) to its target.
Unknown
- Reference: none known.