MIPS Arithmetic, Logic and Shifts

Introduction

Encodings are written most significant bit first; a name is a register or immediate field, a number a fixed bit pattern, and 0s that the manual says must be zero are what makes the word unpredictable when they are not. The ISA column is the first instruction set that has the instruction; “not R6” marks an instruction that Release 6 removes. Add, subtract and the immediate add that end without u raise an overflow exception; those with u do not (the name is historical: the operands are not “unsigned”). Results are sign-extended to 64 bits on a 64-bit processor.

Shifts and rotates

Instruction	Encoding	ISA	What it does
`sll rd, rt, sa`	`000000 0 rt rd sa 000000`	MIPS I	Shift left logical by `sa`. All zero fields is `nop`; `sll $0,$0,1` is `ssnop`, 3 is `ehb`, 5 is `pause`.
`srl rd, rt, sa`	`000000 0 rt rd sa 000010`	MIPS I	Shift right logical.
`sra rd, rt, sa`	`000000 0 rt rd sa 000011`	MIPS I	Shift right arithmetic (the sign bit fills in).
`sllv rd, rt, rs`	`000000 rs rt rd 0 000100`	MIPS I	Shift left by the low five bits of `rs`.
`srlv rd, rt, rs`	`000000 rs rt rd 0 000110`	MIPS I	Shift right logical by a register.
`srav rd, rt, rs`	`000000 rs rt rd 0 000111`	MIPS I	Shift right arithmetic by a register.
`rotr rd, rt, sa`	`000000 00001 rt rd sa 000010`	Release 2	Rotate right (the encoding of `srl` with bit 21 set).
`rotrv rd, rt, rs`	`000000 rs rt rd 00001 000110`	Release 2	Rotate right by a register.
`dsll rd, rt, sa`	`000000 0 rt rd sa 111000`	MIPS III	64-bit shift left by 0 to 31.
`dsrl rd, rt, sa`	`000000 0 rt rd sa 111010`	MIPS III	64-bit shift right logical by 0 to 31.
`dsra rd, rt, sa`	`000000 0 rt rd sa 111011`	MIPS III	64-bit shift right arithmetic by 0 to 31.
`dsll32 rd, rt, sa`	`000000 0 rt rd sa 111100`	MIPS III	64-bit shift left by 32 + `sa`.
`dsrl32 rd, rt, sa`	`000000 0 rt rd sa 111110`	MIPS III	64-bit shift right logical by 32 + `sa`.
`dsra32 rd, rt, sa`	`000000 0 rt rd sa 111111`	MIPS III	64-bit shift right arithmetic by 32 + `sa`.
`dsllv rd, rt, rs`	`000000 rs rt rd 0 010100`	MIPS III	64-bit shift left by the low six bits of `rs`.
`dsrlv rd, rt, rs`	`000000 rs rt rd 0 010110`	MIPS III	64-bit shift right logical by a register.
`dsrav rd, rt, rs`	`000000 rs rt rd 0 010111`	MIPS III	64-bit shift right arithmetic by a register.
`drotr rd, rt, sa`	`000000 00001 rt rd sa 111010`	MIPS64 Release 2	64-bit rotate right by 0 to 31.
`drotr32 rd, rt, sa`	`000000 00001 rt rd sa 111110`	MIPS64 Release 2	64-bit rotate right by 32 + `sa`.
`drotrv rd, rt, rs`	`000000 rs rt rd 00001 010110`	MIPS64 Release 2	64-bit rotate right by a register.
`lsa rd, rs, rt, sa`	`000000 rs rt rd 000 sa2 000101`	Release 6	`rd = (rs << (sa2+1)) + rt`, 32-bit: the scaled index of an array access.
`dlsa rd, rs, rt, sa`	`000000 rs rt rd 000 sa2 010101`	Release 6, 64-bit	The 64-bit `lsa`.

Conditional moves and selects

Instruction	Encoding	ISA	What it does
`movz rd, rs, rt`	`000000 rs rt rd 0 001010`	MIPS IV, MIPS32 (not R6)	Move `rs` to `rd` if `rt` is zero.
`movn rd, rs, rt`	`000000 rs rt rd 0 001011`	MIPS IV, MIPS32 (not R6)	Move if `rt` is not zero.
`movf rd, rs, cc`	`000000 rs cc 0 0 rd 0 000001`	MIPS IV, MIPS32 (not R6)	Move if floating-point condition code `cc` is false.
`movt rd, rs, cc`	`000000 rs cc 0 1 rd 0 000001`	MIPS IV, MIPS32 (not R6)	Move if condition code `cc` is true.
`seleqz rd, rs, rt`	`000000 rs rt rd 00000 110101`	Release 6	`rd = rt == 0 ? rs : 0` (replaces `movz`).
`selnez rd, rs, rt`	`000000 rs rt rd 00000 110111`	Release 6	`rd = rt != 0 ? rs : 0` (replaces `movn`).

Add, subtract, compare, logic

Instruction	Encoding	ISA	What it does
`add rd, rs, rt`	`000000 rs rt rd 0 100000`	MIPS I	Add; an overflow raises an exception.
`addu rd, rs, rt`	`000000 rs rt rd 0 100001`	MIPS I	Add without an overflow exception. `move rd, rs` is `addu rd, rs, $0`.
`sub rd, rs, rt`	`000000 rs rt rd 0 100010`	MIPS I	Subtract; overflow raises an exception.
`subu rd, rs, rt`	`000000 rs rt rd 0 100011`	MIPS I	Subtract without an overflow exception.
`and rd, rs, rt`	`000000 rs rt rd 0 100100`	MIPS I	Bitwise and.
`or rd, rs, rt`	`000000 rs rt rd 0 100101`	MIPS I	Bitwise or. `or rd, rs, $0` is `move`.
`xor rd, rs, rt`	`000000 rs rt rd 0 100110`	MIPS I	Bitwise exclusive or.
`nor rd, rs, rt`	`000000 rs rt rd 0 100111`	MIPS I	Bitwise not-or. `nor rd, rs, $0` is `not`.
`slt rd, rs, rt`	`000000 rs rt rd 0 101010`	MIPS I	`rd = 1` if `rs < rt` (signed), else 0.
`sltu rd, rs, rt`	`000000 rs rt rd 0 101011`	MIPS I	The same, unsigned.
`dadd rd, rs, rt`	`000000 rs rt rd 0 101100`	MIPS III	64-bit add with an overflow exception.
`daddu rd, rs, rt`	`000000 rs rt rd 0 101101`	MIPS III	64-bit add without it.
`dsub rd, rs, rt`	`000000 rs rt rd 0 101110`	MIPS III	64-bit subtract with an overflow exception.
`dsubu rd, rs, rt`	`000000 rs rt rd 0 101111`	MIPS III	64-bit subtract without it.
`addi rt, rs, imm`	`001000 rs rt imm16`	MIPS I (not R6)	Add a sign-extended 16-bit immediate; overflow raises an exception.
`addiu rt, rs, imm`	`001001 rs rt imm16`	MIPS I	Add the immediate without an overflow exception: the usual way to load a small constant or adjust `$sp`.
`slti rt, rs, imm`	`001010 rs rt imm16`	MIPS I	`rt = 1` if `rs` < the sign-extended immediate (signed).
`sltiu rt, rs, imm`	`001011 rs rt imm16`	MIPS I	The same, unsigned compare of the sign-extended immediate.
`andi rt, rs, imm`	`001100 rs rt imm16`	MIPS I	And with the zero-extended immediate.
`ori rt, rs, imm`	`001101 rs rt imm16`	MIPS I	Or with the zero-extended immediate.
`xori rt, rs, imm`	`001110 rs rt imm16`	MIPS I	Exclusive or with the zero-extended immediate.
`daddi rt, rs, imm`	`011000 rs rt imm16`	MIPS III (not R6)	64-bit add immediate with an overflow exception.
`daddiu rt, rs, imm`	`011001 rs rt imm16`	MIPS III	64-bit add immediate without it.
`lui rt, imm`	`001111 0 rt imm16`	MIPS I (not R6)	Load the immediate into the upper 16 bits of `rt`, clearing the low 16. With `ori` or `addiu` it builds a 32-bit constant.
`aui rt, rs, imm`	`001111 rs rt imm16`	Release 6	`rt = rs + (imm << 16)`; with `rs` = 0 it is `lui`.
`daui rt, rs, imm`	`011101 rs rt imm16`	Release 6, 64-bit	`rt = rs + (imm << 16)` sign-extended to 64 bits.
`dahi rs, imm`	`000001 rs 00110 imm16`	Release 6, 64-bit	`rs += imm << 32`.
`dati rs, imm`	`000001 rs 11110 imm16`	Release 6, 64-bit	`rs += imm << 48`.
`addiupc rs, offset`	`111011 rs 00 imm19`	Release 6	`rs = pc + (offset << 2)`. llvm calls it `lapc`.
`auipc rs, imm`	`111011 rs 11110 imm16`	Release 6	`rs = pc + (imm << 16)`, sign-extended.
`aluipc rs, imm`	`111011 rs 11111 imm16`	Release 6	The same with the low 16 bits cleared: the high half of a PC-relative address.

Multiply, divide and HI/LO

Before Release 6 the multiply and divide instructions write the pair HI:LO and mfhi, mflo read it. Release 6 removes HI and LO and gives each result its own register: the encodings below with a nonzero sa field.

Instruction	Encoding	ISA	What it does
`mult rs, rt`	`000000 rs rt 0 011000`	MIPS I (not R6)	Signed 32 × 32 → 64: HI:LO.
`multu rs, rt`	`000000 rs rt 0 011001`	MIPS I (not R6)	Unsigned.
`div rs, rt` / `div rd, rs, rt`	`000000 rs rt 0 011010` / `000000 rs rt rd 00010 011010`	MIPS I (not R6) / Release 6	Signed divide. Before R6: LO = quotient, HI = remainder, and a divide by zero leaves them undefined with no exception. R6: `rd` = the quotient.
`divu rs, rt` / `divu rd, rs, rt`	`000000 rs rt 0 011011` / `… 00010 011011`	MIPS I (not R6) / Release 6	Unsigned divide.
`mul rd, rs, rt`	`011100 rs rt rd 0 000010` / R6 `000000 rs rt rd 00010 011000`	MIPS32 / Release 6	The low 32 bits of the product in a register (HI and LO undefined before R6).
`muh rd, rs, rt`	`000000 rs rt rd 00011 011000`	Release 6	The high 32 bits of the signed product.
`mulu rd, rs, rt`	`000000 rs rt rd 00010 011001`	Release 6	The low 32 bits of the unsigned product.
`muhu rd, rs, rt`	`000000 rs rt rd 00011 011001`	Release 6	The high 32 bits of the unsigned product.
`mod rd, rs, rt`	`000000 rs rt rd 00011 011010`	Release 6	The signed remainder.
`modu rd, rs, rt`	`000000 rs rt rd 00011 011011`	Release 6	The unsigned remainder.
`dmult rs, rt`	`000000 rs rt 0 011100`	MIPS III (not R6)	Signed 64 × 64 → 128: HI:LO.
`dmultu rs, rt`	`000000 rs rt 0 011101`	MIPS III (not R6)	Unsigned.
`ddiv rs, rt` / `ddiv rd, rs, rt`	`000000 rs rt 0 011110` / `… 00010 011110`	MIPS III (not R6) / Release 6	Signed 64-bit divide.
`ddivu rs, rt` / `ddivu rd, rs, rt`	`000000 rs rt 0 011111` / `… 00010 011111`	MIPS III (not R6) / Release 6	Unsigned 64-bit divide.
`dmul rd, rs, rt`	`000000 rs rt rd 00010 011100`	Release 6, 64-bit	The low 64 bits of the signed product.
`dmuh rd, rs, rt`	`000000 rs rt rd 00011 011100`	Release 6, 64-bit	The high 64 bits of the signed product.
`dmulu rd, rs, rt`	`000000 rs rt rd 00010 011101`	Release 6, 64-bit	The low 64 bits of the unsigned product.
`dmuhu rd, rs, rt`	`000000 rs rt rd 00011 011101`	Release 6, 64-bit	The high 64 bits of the unsigned product.
`dmod rd, rs, rt`	`000000 rs rt rd 00011 011110`	Release 6, 64-bit	The signed 64-bit remainder.
`dmodu rd, rs, rt`	`000000 rs rt rd 00011 011111`	Release 6, 64-bit	The unsigned 64-bit remainder.
`mfhi rd`	`000000 0 rd 0 010000`	MIPS I (not R6)	Copy HI to `rd`.
`mflo rd`	`000000 0 rd 0 010010`	MIPS I (not R6)	Copy LO to `rd`.
`mthi rs`	`000000 rs 0 010001`	MIPS I (not R6)	Copy `rs` to HI.
`mtlo rs`	`000000 rs 0 010011`	MIPS I (not R6)	Copy `rs` to LO.
`madd rs, rt`	`011100 rs rt 0 000000`	MIPS32 (not R6)	HI:LO += the signed product.
`maddu rs, rt`	`011100 rs rt 0 000001`	MIPS32 (not R6)	HI:LO += the unsigned product.
`msub rs, rt`	`011100 rs rt 0 000100`	MIPS32 (not R6)	HI:LO −= the signed product.
`msubu rs, rt`	`011100 rs rt 0 000101`	MIPS32 (not R6)	HI:LO −= the unsigned product.
`clz rd, rs`	`011100 rs rd rd 0 100000` / R6 `000000 rs 0 rd 00001 010000`	MIPS32 / Release 6	Count leading zeros. Before R6 the `rt` field must equal `rd`.
`clo rd, rs`	`011100 rs rd rd 0 100001` / R6 `… 00001 010001`	MIPS32 / Release 6	Count leading ones.
`dclz rd, rs`	`011100 rs rd rd 0 100100` / R6 `… 00001 010010`	MIPS64 / Release 6	Count leading zeros of a 64-bit value.
`dclo rd, rs`	`011100 rs rd rd 0 100101` / R6 `… 00001 010011`	MIPS64 / Release 6	Count leading ones of a 64-bit value.

Bit fields and byte order (Release 2 and later)

Instruction	Encoding	ISA	What it does
`ext rt, rs, pos, size`	`011111 rs rt size-1 pos 000000`	Release 2	Extract `size` bits at `pos` of `rs`, zero-extended.
`dext rt, rs, pos, size`	`011111 rs rt size-1 pos 000011`	MIPS64 Release 2	Extract a field of 1 to 32 bits.
`dextm rt, rs, pos, size`	`011111 rs rt size-33 pos 000001`	MIPS64 Release 2	Extract a field of 33 to 64 bits. Disassembled as `dext` with the aliases on.
`dextu rt, rs, pos, size`	`011111 rs rt size-1 pos-32 000010`	MIPS64 Release 2	Extract a field that starts at bit 32 to 63.
`ins rt, rs, pos, size`	`011111 rs rt pos+size-1 pos 000100`	Release 2	Insert the low `size` bits of `rs` at `pos` of `rt`.
`dins rt, rs, pos, size`	`011111 rs rt pos+size-1 pos 000111`	MIPS64 Release 2	Insert a field that fits in the low 32 bits.
`dinsm rt, rs, pos, size`	`011111 rs rt pos+size-33 pos 000101`	MIPS64 Release 2	Insert a field that ends above bit 31.
`dinsu rt, rs, pos, size`	`011111 rs rt pos+size-33 pos-32 000110`	MIPS64 Release 2	Insert a field that starts at bit 32 to 63.
`wsbh rd, rt`	`011111 0 rt rd 00010 100000`	Release 2	Swap the bytes within each halfword. With `rotr 16` it byte-swaps a word.
`seb rd, rt`	`011111 0 rt rd 10000 100000`	Release 2	Sign-extend the low byte.
`seh rd, rt`	`011111 0 rt rd 11000 100000`	Release 2	Sign-extend the low halfword.
`dsbh rd, rt`	`011111 0 rt rd 00010 100100`	MIPS64 Release 2	Swap the bytes within each halfword of a doubleword.
`dshd rd, rt`	`011111 0 rt rd 00101 100100`	MIPS64 Release 2	Swap the halfwords of a doubleword.
`bitswap rd, rt`	`011111 0 rt rd 00000 100000`	Release 6	Reverse the bits within each byte.
`dbitswap rd, rt`	`011111 0 rt rd 00000 100100`	Release 6, 64-bit	The same for a doubleword.
`align rd, rs, rt, bp`	`011111 rs rt rd 010 bp2 100000`	Release 6	Take 32 bits from the concatenation `rt:rs`, shifted by `bp` bytes.
`dalign rd, rs, rt, bp`	`011111 rs rt rd 01 bp3 100100`	Release 6, 64-bit	The same for 64 bits.
`rdhwr rt, rd`	`011111 0 rt rd 0 111011`	Release 2	Read a hardware register: 0 the CPU number, 1 the SYNCI step, 2 the cycle counter, 3 its resolution, 29 the thread pointer (what thread-local storage uses).

Traps and system calls

Instruction	Encoding	ISA	What it does
`syscall [code]`	`000000 code20 001100`	MIPS I	System call exception; the operating system reads the 20-bit code (or the registers) to say which call.
`break [code1[, code2]]`	`000000 code10 code10 001101`	MIPS I	Breakpoint exception. Compilers use `break 7` after a divide by a constant zero check, `break 6` for a range error.
`sdbbp [code]`	`011100 code20 111111` / R6 `000000 code20 001110`	MIPS32 / Release 6	Software debug breakpoint: enters debug mode.
`sync [stype]`	`000000 0 stype 001111`	MIPS II	Order loads and stores: those before it complete before those after it. `stype` 0 is the full barrier; Release 2 adds finer types.
`tge rs, rt`	`000000 rs rt code10 110000`	MIPS II	Trap if `rs` ≥ `rt` (signed).
`tgeu rs, rt`	`000000 rs rt code10 110001`	MIPS II	Trap if ≥ (unsigned).
`tlt rs, rt`	`000000 rs rt code10 110010`	MIPS II	Trap if < (signed).
`tltu rs, rt`	`000000 rs rt code10 110011`	MIPS II	Trap if < (unsigned).
`teq rs, rt`	`000000 rs rt code10 110100`	MIPS II	Trap if equal. Compilers use `teq $rt, $0, 7` to trap a divide by zero.
`tne rs, rt`	`000000 rs rt code10 110110`	MIPS II	Trap if not equal.
`tgei rs, imm`	`000001 rs 01000 imm16`	MIPS II (not R6)	Trap if `rs` ≥ the sign-extended immediate.
`tgeiu rs, imm`	`000001 rs 01001 imm16`	MIPS II (not R6)	Unsigned.
`tlti rs, imm`	`000001 rs 01010 imm16`	MIPS II (not R6)	Trap if < the immediate.
`tltiu rs, imm`	`000001 rs 01011 imm16`	MIPS II (not R6)	Unsigned.
`teqi rs, imm`	`000001 rs 01100 imm16`	MIPS II (not R6)	Trap if equal to the immediate.
`tnei rs, imm`	`000001 rs 01110 imm16`	MIPS II (not R6)	Trap if not equal.
`sigrie [code]`	`000001 0 10111 code16`	Release 6	Signal a reserved instruction exception: the way to deliberately trap.

On a MIPS I processor (the PlayStation) the trap instructions are not defined and compilers use break for the checks.

Cache and prefetch

Instruction	Encoding	ISA	What it does
`cache op, offset(base)`	`101111 base op offset16` / R6 `011111 base op offset9 0 100101`	MIPS III, MIPS32 / Release 6	Perform a cache operation (invalidate, write back, fill, set a tag) at the address. `op` says the cache and the operation.
`pref hint, offset(base)`	`110011 base hint offset16` / R6 `011111 base hint offset9 0 110101`	MIPS IV, MIPS32 / Release 6	Prefetch hint: a processor may bring the line into the cache or ignore it.
`synci offset(base)`	`000001 base 11111 offset16`	Release 2	Make the instructions written at the address visible to instruction fetch (after a code write). Cheaper than a `cache` loop and allowed in user mode.
`nal`	`000001 0 10000 0…0`	Release 6	Put the address after the delay slot in `$ra` without jumping: the way to get the program counter. (Before R6 it is `bltzal $0` with an offset.)
`bal offset`	`000001 0 10001 offset16`	Release 6 (an alias of `bgezal $0` before)	Branch and link, always. See Jumps and branches.

Not described

Known, not yet covered

Reference: the DSP ASE integer instructions (addu.qb, mfhi with DSP accumulators and so on) and the MT, MSA and VZ extensions; the R5900 and Allegrex extras.
Reference: the exact exception behaviour of each instruction (overflow, address error, reserved instruction); these pages describe the result only.

Unknown

Reference: none known.