NEC V810 Instruction Set – Status and what is not described

Statuses

Counted over every first halfword with one second halfword (all 64 sub-opcodes for opcode 0x3E): 71,168 documented, 1,920 reserved, 56,960 illegal.

What the checks found

• Written tables (test-v810-tables.mjs): the two hand-written tables agree with each other and with the decoder on 247,808 pairs: 1,465,856 checks, 0 failures.
• The site’s small disassembler (emulators.org/debugger/src/cpus/v810.js, test-v810-debugger.mjs): 271,360 pairs, 0 unexplained differences. Counted differences that are its choices: it prints .word for 69,248 undefined encodings (including the bit-string sub-opcodes 0x10–0x1F); it calls SETF condition 5 R and condition 13 nothing (ours T and F): 128; it prints XB and XH with two operands: 2,048; it keeps bit 0 of an odd branch or jump displacement in the target: 12,032.
• The site’s Virtual Boy core (vb-core.js, test-v810-core.mjs): 313,206 instructions run from random states, 3,476,945 checks, 0 failures. Known difference: it does not clear bit 0 of an odd target (16,276 runs). The core does not model bit-strings, floating point, CAXI, TRAP, RETI, HALT, division by zero or the undefined opcodes, so those are checked by the tables only; its PSW is simplified, so LDSR/STSR of the PSW are not run. It is not an independent third party: it was written for the same site.
• The demo ROM (test-v810-demo.mjs): the 28 instructions and the reset vector of the 1 KiB program decode to what its assembler source says: 89 checks.
• The effect lists of the multiply and divide instructions put the high word or the remainder in r30 (the core and the Mednafen summary agree). An early draft of our table said OV is always cleared by MUL; the Mednafen summary says it is set when the product does not fit, and the table was corrected.

Not described

Known, not yet covered

• Clock counts: the Mednafen core as read has per-instruction timings (for example 1 for NOP and HALT, 3 for a taken branch or jump, 13 for MUL, 38 for DIV, 15 for TRAP, 10 for RETI, 26 for CAXI, and increments for the floating-point group), but they were read through summaries and no second source was read, so the decoder gives none.
• The system registers 29 to 31 and the PSW interrupt-mask rule: named in some documents, not in the sources read.
• The exact semantics of the bit-string instructions (register roles, search results, flags, restart state) and the flags of XB XH REV MPYHW.
• Floating-point details: rounding, denormals, which exception flags each instruction can set, the exception vector layout beyond the addresses listed on the viewer’s page.

Unknown

• The manual itself. The NEC V810 Family User’s Manual and the Sacred Tech Scroll could not be read here (the site refused the connection; the other pages returned only a landing page). Every encoding rests on the Mednafen core’s opcode enumeration and the binutils thread as read through summaries, on memory, and on the checks above.
• NVC against V810. Whether the Virtual Boy’s NVC lacks or adds instructions compared with the plain V810 is not stated in the sources read (the Mednafen core enables XB XH REV MPYHW only in its Virtual Boy mode). The decoder has one variant.
• Whether the unused fields must be zero: the low ten bits of the extended second halfword, reg1 of XB/XH, reg1 and reg2 of CLI/RETI/HALT/SEI, and the register field of a bit-string instruction. The decoder accepts any value (the extended case adds a note).