Primary opcodes
The opcode is bits 15 to 10 of the first halfword. The row gives the opcode of the first column; add the column number. The format is in brackets; opcodes 0x20–0x27 are all Bcond (the condition’s top three bits are part of the opcode).
Cells marked undefined have the status illegal.
| Opcode | +0 | +1 | +2 | +3 | +4 | +5 | +6 | +7 |
|---|---|---|---|---|---|---|---|---|
0x00 | MOV (I) | ADD (I) | SUB (I) | CMP (I) | SHL (I) | SHR (I) | JMP (I) | SAR (I) |
0x08 | MUL (I) | DIV (I) | MULU (I) | DIVU (I) | OR (I) | AND (I) | XOR (I) | NOT (I) |
0x10 | MOV (II) | ADD (II) | SETF (II) | CMP (II) | SHL (II) | SHR (II) | CLI (II) | SAR (II) |
0x18 | TRAP (II) | RETI (II) | HALT (II) | undefined | LDSR (II) | STSR (II) | SEI (II) | BSTR (II) |
0x20 | Bcond (III) | Bcond (III) | Bcond (III) | Bcond (III) | Bcond (III) | Bcond (III) | Bcond (III) | Bcond (III) |
0x28 | MOVEA (V) | ADDI (V) | JR (IV) | JAL (IV) | ORI (V) | ANDI (V) | XORI (V) | MOVHI (V) |
0x30 | LD.B (VI) | LD.H (VI) | undefined | LD.W (VI) | ST.B (VI) | ST.H (VI) | undefined | ST.W (VI) |
0x38 | IN.B (VI) | IN.H (VI) | CAXI (VI) | IN.W (VI) | OUT.B (VI) | OUT.H (VI) | EXT (VII) | OUT.W (VI) |
Three opcodes are undefined: 0x1B, 0x32 and 0x36. BSTR is the bit-string group (below) and EXT the floating-point and extended group.
Bit-string sub-opcodes (opcode 0x1F, the low five bits)
| Sub | +0 | +1 | +2 | +3 | +4 | +5 | +6 | +7 |
|---|---|---|---|---|---|---|---|---|
0x00 | SCH0BSU | SCH0BSD | SCH1BSU | SCH1BSD | undefined | undefined | undefined | undefined |
0x08 | ORBSU | ANDBSU | XORBSU | MOVBSU | ORNBSU | ANDNBSU | XORNBSU | NOTBSU |
0x10 | undefined | undefined | undefined | undefined | undefined | undefined | undefined | undefined |
0x18 | undefined | undefined | undefined | undefined | undefined | undefined | undefined | undefined |
Extended sub-opcodes (opcode 0x3E, bits 15 to 10 of the second halfword)
| Sub | +0 | +1 | +2 | +3 | +4 | +5 | +6 | +7 |
|---|---|---|---|---|---|---|---|---|
0x00 | CMPF.S | undefined | CVT.WS | CVT.SW | ADDF.S | SUBF.S | MULF.S | DIVF.S |
0x08 | XB | XH | REV | TRNC.SW | MPYHW | undefined | undefined | undefined |
0x10 to 0x38 | undefined (all 40 sub-opcodes) | |||||||
Bcond conditions
The condition is bits 12 to 9 of the first halfword; the table is on the registers page. Condition 13 is NOP.
Not described
See the status page: which of the opcodes above exist on the Virtual Boy’s NVC but not on the plain V810 (or the reverse) is not stated in the sources read.