Encoding
These are format VII instructions: four bytes, the first halfword 111110 reg2(5) reg1(5), the second halfword subopcode(6) unused(10). The sub-opcode is bits 15 to 10 of the second halfword;
0x01 and 0x0D to 0x3F are undefined (the core as read raises the invalid-opcode exception). In the table the second halfword is therefore sub << 10: the binutils entry two(0xf800, 0x1000) for ADDF.S has sub-opcode 0x04.
Floating-point values are IEEE 754 single precision held in a general register.
Floating-point
| Mnemonic | Operands | Sub-opcode | Operation | Flags | Exception flags it can set |
|---|---|---|---|---|---|
CMPF.S | r1,r2 | 0x00 | Compare: the flags of r2 - r1; nothing is stored | Z S OV CY | FRO |
CVT.WS | r1,r2 | 0x02 | r2 = r1 (a signed integer) as a float | Z S OV CY | FPR |
CVT.SW | r1,r2 | 0x03 | r2 = r1 (a float) as a signed integer, rounded | Z S OV CY | FRO FIV FPR |
ADDF.S | r1,r2 | 0x04 | r2 = r2 + r1 | Z S OV CY | FRO FOV FUD FPR |
SUBF.S | r1,r2 | 0x05 | r2 = r2 - r1 | Z S OV CY | FRO FOV FUD FPR |
MULF.S | r1,r2 | 0x06 | r2 = r2 * r1 | Z S OV CY | FRO FOV FUD FPR |
DIVF.S | r1,r2 | 0x07 | r2 = r2 / r1 | Z S OV CY | FRO FZD FOV FUD FPR |
TRNC.SW | r1,r2 | 0x0B | r2 = r1 (a float) as a signed integer, truncated toward zero | Z S OV CY | FRO FIV |
The flag letters and the exception-flag column are from memory of the NEC manual and were not checked against a source read; the Mednafen core as read only confirms the instruction names and the sub-opcodes, and gives its own timing increments (not listed here).
Unknown in the sources read: the rounding mode, denormal handling, and whether the exception flags trap (the floating-point exception vector 0xFFFFFF60 is the one the core as read uses).
Extended integer instructions
The Mednafen core handles these four only when it emulates the Virtual Boy; they are in the Virtual Boy documentation, and the decoder treats them as ordinary instructions. XB and XH have one register operand (the reg1 field is not used).
| Mnemonic | Operands | Sub-opcode | Operation | Flags |
|---|---|---|---|---|
XB | r2 | 0x08 | Exchange the two low bytes of r2 | not stated |
XH | r2 | 0x09 | Exchange the two halfwords of r2 | not stated |
REV | r1,r2 | 0x0A | r2 = r1 with its 32 bits in reverse order | not stated |
MPYHW | r1,r2 | 0x0C | r2 = r2 * r1 with both taken as signed 16-bit halves (a 32-bit product) | not stated |
Not described
See the status page: the flags of the four extended instructions, the floating-point flag details and rounding, and the clock counts.