General registers
There are 32 registers of 32 bits, r0 to r31. r0 always reads as zero and a write to it is lost (the decoder leaves it out of the registers an instruction reads or writes).
The program counter is separate. Hardware gives a few registers a job; the rest are a convention of the Virtual Boy compilers, which the viewer can show as names (the option “Register names”).
| Register | Name | Use |
|---|---|---|
r0 | zero | Always 0 (hardware) |
r1 | hp | Handler pointer (convention) |
r2 | fp | Frame pointer (convention) |
r3 | sp | Stack pointer (convention) |
r4 | gp | Global pointer: small data (convention) |
r5 | tp | Text pointer (convention) |
r6 to r25 | General use (arguments, results, temporaries and saved registers by the compilers’ rules) | |
r26 to r29 | The bit-string instructions use them (with r30) as their operands, so a program that uses those instructions cannot keep other values in them | |
r30 | ep | Element pointer (convention); MUL, MULU, DIV, DIVU put the high word or the remainder here; CAXI reads the value to store from it |
r31 | lp | Link pointer: JAL puts the return address here (hardware) |
System registers
LDSR and STSR name a system register by a 5-bit number. Only the numbers below are named in the sources read; the others (8 to 23, 26 to 31) are shown as SRn with the status reserved.
| No. | Name | Meaning |
|---|---|---|
| 0 | EIPC | Exception/interrupt PC: the PC saved when an exception or interrupt is taken |
| 1 | EIPSW | Exception/interrupt PSW: the PSW saved with it |
| 2 | FEPC | Fatal-error PC: saved by a duplexed exception (an exception during an exception) and by the NMI |
| 3 | FEPSW | Fatal-error PSW |
| 4 | ECR | Exception cause register: the code of the last exception or interrupt (low half) and of the last fatal one (high half) |
| 5 | PSW | Program status word (below) |
| 6 | PIR | Processor ID, read only |
| 7 | TKCW | Task control word: floating-point control, read only |
| 24 | CHCW | Cache control word: instruction cache enable, clear and dump |
| 25 | ADTRE | Address trap register for execution |
The PSW
| Bit | Name | Meaning |
|---|---|---|
| 0 | Z | Zero |
| 1 | S | Sign |
| 2 | OV | Overflow |
| 3 | CY | Carry (or borrow) |
| 4 | FRO | Floating-point reserved operand |
| 5 | FIV | Floating-point invalid operation |
| 6 | FZD | Floating-point divide by zero |
| 7 | FOV | Floating-point overflow |
| 8 | FUD | Floating-point underflow |
| 9 | FPR | Floating-point precision degradation |
| 12 | ID | Interrupt disable: set by SEI, cleared by CLI |
| 13 | AE | Address trap enable |
| 14 | EP | Exception pending |
| 15 | NP | NMI pending: selects FEPC/FEPSW for RETI |
| 16–19 | I | Interrupt mask level (4 bits; taking an interrupt sets it to its own level plus one; the comparison rule is not described here) |
The bit positions of ID, AE, EP and NP and the mask field are from memory of the NEC manual; the flag bits 0 to 9 agree with the Mednafen core’s constants as read.
Condition codes
Bits 12 to 9 of a branch, and the low four bits of the SETF operand, choose one of sixteen conditions. The manual names the carry and zero tests two ways (BL/BC, BE/BZ,
BNL/BNC, BNE/BNZ); the viewer’s option “Condition names” picks the spelling. SETF writes T and F for codes 5 and 13, where the branch is BR and NOP.
| Code | Branch | SETF | True when |
|---|---|---|---|
| 0 | BV | V | OV = 1 |
| 1 | BL / BC | L / C | CY = 1 |
| 2 | BE / BZ | E / Z | Z = 1 |
| 3 | BNH | NH | CY = 1 or Z = 1 |
| 4 | BN | N / S | S = 1 |
| 5 | BR | T | always |
| 6 | BLT | LT | S xor OV = 1 |
| 7 | BLE | LE | (S xor OV) or Z |
| 8 | BNV | NV | OV = 0 |
| 9 | BNL / BNC | NL / NC | CY = 0 |
| 10 | BNE / BNZ | NE / NZ | Z = 0 |
| 11 | BH | H | CY = 0 and Z = 0 |
| 12 | BP | P / NS | S = 0 |
| 13 | NOP | F | never |
| 14 | BGE | GE | S xor OV = 0 |
| 15 | BGT | GT | (S xor OV) or Z = 0 |
Not described
See the status page: system registers 8 to 23 and 26 to 31, the exact PSW interrupt-mask field and the reset values of the registers are not covered.