Halfwords and length
An instruction is one or two 16-bit halfwords, stored low byte first. Bits 15 to 10 of the first halfword are the opcode. When bits 15 to 13 are 101 or 11x (opcode 0x28 and up) the instruction is four bytes
and the second halfword follows; every other instruction is two bytes. Instructions start at even addresses. The viewer decodes at every even offset, so overlapping decodes (a four-byte instruction and the one starting at its second halfword) appear in two columns.
An undefined encoding is shown as a two-byte .HALF whatever its format would have been, so that the next halfword is decoded on its own: the CPU never executes past it.
The seven formats
| Format | Length | First halfword (bit 15 left) | Second halfword | Used by |
|---|---|---|---|---|
| I | 2 | opcode(6) reg2(5) reg1(5) | – | Register to register: MOV ADD SUB CMP SHL SHR JMP SAR MUL DIV MULU DIVU OR AND XOR NOT (opcodes 0x00–0x0F; JMP uses only reg1) |
| II | 2 | opcode(6) reg2(5) imm5(5) | – | Immediate and system: MOV ADD SETF CMP SHL SHR SAR with imm5, CLI TRAP RETI HALT LDSR STSR SEI and the bit-string group (opcodes 0x10–0x1F; for LDSR/STSR the 5-bit field is the system register number, for TRAP the vector, for the bit-strings the sub-opcode) |
| III | 2 | 100 cond(4) disp(9) | – | Conditional branches (opcodes 0x20–0x27: the top three bits 100 are the opcode, the next four the condition, the low nine a signed displacement) |
| IV | 4 | opcode(6) disp26 high (10) | disp26 low (16) | JR (0x2A) and JAL (0x2B) |
| V | 4 | opcode(6) reg2(5) reg1(5) | imm16 | MOVEA ADDI ORI ANDI XORI MOVHI (opcodes 0x28, 0x29, 0x2C–0x2F) |
| VI | 4 | opcode(6) reg2(5) reg1(5) | disp16 | Load, store, I/O and CAXI (opcodes 0x30–0x3D and 0x3F) |
| VII | 4 | 111110 reg2(5) reg1(5) | subopcode(6) unused(10) | The extended group, opcode 0x3E: floating-point, XB XH REV MPYHW |
Branch and jump targets
- Format III. target = the address of the branch + the 9-bit displacement sign-extended from bit 8, with bit 0 cleared. The displacement counts from the first byte of the branch itself, not from the next instruction.
- Format IV. target = the address of the
JRorJAL+ the 26-bit displacement (the 10 low bits of the first halfword are its high bits) sign-extended, bit 0 cleared.JALstores the address four bytes after itself inr31. - JMP. target =
r1with bit 0 cleared; the decoder cannot know it.
The clearing of bit 0 follows the Mednafen core as read through a summary; the site’s own small disassembler does not clear it; that is the only difference found for odd displacements.
Immediates and displacements
imm5is sign-extended inMOV,ADDandCMP(−16 to 15) and unsigned in the shifts andTRAP.imm16ofMOVEAandADDIis sign-extended; ofORI,ANDI,XORIandMOVHIit is used as 16 bits (MOVHIshifts it into the high half).disp16of the memory instructions is sign-extended and added tor1; withr1 = r0it is an absolute address from −32768 to 32767, which the viewer names when it matches a hardware register or a ROM top address (the high mirror of the ROM is reached that way).
Not described
See the status page: whether the unused bits of the extended second halfword and of the one-operand formats must be zero is not stated in the sources read, so the decoder accepts any value.