Reading the tables
None of these instructions changes a flag. Cycles are those of the classic cores. A register that receives data is Rd, one that is stored Rr. “Data space” is the
space of the registers, I/O and RAM. Instructions of the data space need the core to have RAM (not avr1).
Between registers, and constants
| Instruction | Encoding | Operation | Cycles | Cores |
|---|---|---|---|---|
MOV Rd,Rr | 0010 11rd dddd rrrr | Rd ← Rr. | 1 | All |
MOVW Rd+1:Rd,Rr+1:Rr | 0000 0001 dddd rrrr | Copies a register pair; both registers are even. | 1 | avr25, avr35, avr4 and above |
LDI Rd,K | 1110 KKKK dddd KKKK | Rd ← K (r16 to r31). SER Rd is LDI Rd,0xFF. | 1 | All |
Loads and stores of the data space
| Instruction | Encoding | Operation | Cycles |
|---|---|---|---|
LD Rd,X · X+ · -X | 1001 000d dddd 1100 · 1101 · 1110 | Rd ← (X); X+ adds one to X afterwards, -X subtracts one first. Likewise with Y (1001 = Y+, 1010 = -Y) and Z (0001 = Z+, 0010 = -Z). LD Rd,Y and LD Rd,Z without change are LDD with displacement 0. | 2 |
LDD Rd,Y+q · Z+q | 10q0 qq0d dddd 1qqq (Y) · 0qqq (Z) | Rd ← (Y + q), q 0 to 63. Not on the reduced core. | 2 |
LDS Rd,k | 1001 000d dddd 0000 + k (16 bits) | Rd ← (k): a direct 16-bit data address. Two words. | 2 |
LDS Rd,k (reduced core) | 1010 0kkk dddd kkkk | Rd ← (0x40 + k), Rd r16 to r31. One word: data addresses 0x40 to 0xBF only. | — |
ST X,Rr · X+ · -X | 1001 001r rrrr 1100 · 1101 · 1110 | (X) ← Rr, with post-increment or pre-decrement; likewise Y and Z (same low nibbles as LD). | 2 |
STD Y+q,Rr · Z+q,Rr | 10q0 qq1r rrrr 1qqq (Y) · 0qqq (Z) | (Y + q) ← Rr, q 0 to 63. Not on the reduced core. | 2 |
STS k,Rr | 1001 001r rrrr 0000 + k (16 bits) | (k) ← Rr. Two words. | 2 |
STS k,Rr (reduced core) | 1010 1kkk rrrr kkkk | (0x40 + k) ← Rr (r16 to r31). One word. | — |
PUSH Rr | 1001 001r rrrr 1111 | (SP) ← Rr, then SP ← SP − 1. | 2 |
POP Rd | 1001 000d dddd 1111 | SP ← SP + 1, then Rd ← (SP). | 2 |
Unpredictable. The manual says the result is undefined when the register loaded or stored by a post-increment or pre-decrement form is one of the pointer’s own registers
(LD r26,X+, LD r27,-X, ST X+,r26, LD r28,Y+, LD r31,-Z and so on). The disassembler marks them unpredictable.
Reading and writing flash
| Instruction | Encoding | Operation | Cycles | Cores |
|---|---|---|---|---|
LPM · LPM Rd,Z · LPM Rd,Z+ | 1001 0101 1100 1000 · 1001 000d dddd 0100 · 0101 | R0 or Rd ← the flash byte at the byte address Z (the low bit of Z picks the byte of the word); Z+ adds one to Z afterwards. | 3 | LPM: every core except the reduced one; Rd,Z forms: avr25, avr35, avr4, avr5, avr51, avr6, XMEGA, tinyAVR 0/1/2 |
ELPM · ELPM Rd,Z · ELPM Rd,Z+ | 1001 0101 1101 1000 · 1001 000d dddd 0110 · 0111 | The same with the address RAMPZ:Z, 24 bits: the flash above 64 KB. | 3 | ELPM: avr31, avr51, avr6, XMEGA; Rd,Z forms: avr51, avr6, XMEGA |
SPM · SPM Z+ | 1001 0101 1110 1000 · 1001 0101 1111 1000 | Writes the register pair R1:R0 into the flash page at Z (self-programming): erase, write, or fill the page buffer, as the SPM control register says. Z+ (XMEGA) adds two to Z afterwards. | depends | avr25, avr35, avr4, avr5, avr51, avr6, XMEGA (Z+: XMEGA); not avr1, avr2, avr3, avr31, tinyAVR 0/1/2 or the reduced core |
XMEGA read-modify-write
Four XMEGA instructions read a data space byte at Z, change it and write it back in one operation (two cycles), leaving the old value in Rr:
| Instruction | Encoding | Operation |
|---|---|---|
XCH Z,Rr | 1001 001r rrrr 0100 | Exchange: (Z) ↔ Rr. |
LAS Z,Rr | 1001 001r rrrr 0101 | Load and set: (Z) ← (Z) OR Rr, Rr ← the old (Z). |
LAC Z,Rr | 1001 001r rrrr 0110 | Load and clear: (Z) ← (Z) AND NOT Rr, Rr ← the old (Z). |
LAT Z,Rr | 1001 001r rrrr 0111 | Load and toggle: (Z) ← (Z) XOR Rr, Rr ← the old (Z). |
I/O space
| Instruction | Encoding | Operation | Cycles |
|---|---|---|---|
IN Rd,A | 1011 0AAd dddd AAAA | Rd ← I/O(A), A 0 to 63. | 1 |
OUT A,Rr | 1011 1AAr rrrr AAAA | I/O(A) ← Rr, A 0 to 63. | 1 |
The viewer can name the I/O registers of four devices (I/O register names).
Not described
- The cycle counts of loads and stores on XMEGA, tinyAVR 0/1/2 and the reduced core (they differ with the addressing mode and with whether the access is to I/O), and the extra cycles of external RAM.
- The effect of
SPM(page erase, write, fill, lock bits) beyond the summary above; the self-programming control register is device-specific.