Shifts and rotates
All take one cycle on every core. LSL Rd and ROL Rd have no encoding of their own: they are ADD Rd,Rd and ADC Rd,Rd (see the
arithmetic page).
| Instruction | Encoding | Operation | Flags |
|---|---|---|---|
LSL Rd | = ADD Rd,Rd | Logical shift left: 0 into bit 0, bit 7 into C. | H S V N Z C |
LSR Rd | 1001 010d dddd 0110 | Logical shift right: 0 into bit 7, bit 0 into C. | S V N Z C |
ROL Rd | = ADC Rd,Rd | Rotate left through the carry: C into bit 0, bit 7 into C. | H S V N Z C |
ROR Rd | 1001 010d dddd 0111 | Rotate right through the carry: C into bit 7, bit 0 into C. | S V N Z C |
ASR Rd | 1001 010d dddd 0101 | Arithmetic shift right: bit 7 stays, bit 0 into C. | S V N Z C |
SWAP Rd | 1001 010d dddd 0010 | Swaps the two nibbles of Rd. | — |
Single bits
| Instruction | Encoding | Operation | Flags | Cycles |
|---|---|---|---|---|
SBI A,b | 1001 1010 AAAA Abbb | Sets bit b of I/O register A (0 to 31). | — | 2 (differs on the other cores) |
CBI A,b | 1001 1000 AAAA Abbb | Clears bit b of I/O register A (0 to 31). | — | 2 (differs on the other cores) |
BST Rd,b | 1111 101d dddd 0bbb | T ← bit b of Rd. | T | 1 |
BLD Rd,b | 1111 100d dddd 0bbb | Bit b of Rd ← T. | — | 1 |
BSET s | 1001 0100 0sss 1000 | Sets bit s of SREG. Written SEC (0), SEZ (1), SEN (2), SEV (3), SES (4), SEH (5), SET (6), SEI (7). | that bit | 1 |
BCLR s | 1001 0100 1sss 1000 | Clears bit s of SREG. Written CLC, CLZ, CLN, CLV, CLS, CLH, CLT, CLI. | that bit | 1 |
Only the classic cores’ count is tabulated by the viewer. The mask-and-set forms with an immediate (SBR, CBR) are ORI and ANDI.
MCU control
| Instruction | Encoding | Operation | Cycles | Cores |
|---|---|---|---|---|
NOP | 0000 0000 0000 0000 | Does nothing. | 1 | All |
SLEEP | 1001 0101 1000 1000 | Puts the device into the sleep mode the sleep control register selects, until an interrupt. | 1 | All |
WDR | 1001 0101 1010 1000 | Resets the watchdog timer. | 1 | All |
BREAK | 1001 0101 1001 1000 | Stops the processor when on-chip debugging is on; otherwise does nothing. | 1 | avr25, avr35, avr4 and above, XMEGA |
Not described
- The sleep modes and the watchdog registers, which are specific to a device.
- The exact timing of
SBIandCBIon the cores other than the classic ones.