Addresses in this page
In the tables PC counts words, as in the manual; the disassembler writes the byte address of the target (words and bytes).
The cycles are those of the classic cores. On a device with a three-byte return address (ATmega2560 and the other devices with more than 128 K words of flash)
RCALL, ICALL, CALL, RET and RETI take one cycle more; the decoder adds it for avr6.
Jumps and calls
| Instruction | Encoding | Operation | Cycles | Cores |
|---|---|---|---|---|
RJMP k | 1100 kkkk kkkk kkkk | PC ← PC + k + 1, k from −2048 to +2047 words. | 2 | All |
JMP k | 1001 010k kkkk 110k + kkkk kkkk kkkk kkkk | PC ← k, a 22-bit word address. Two words. | 3 | With JMP (avr3, avr31, avr35, avr5 and above, XMEGA) |
IJMP | 1001 0100 0000 1001 | PC ← Z (a word address). | 2 | All but avr1 |
EIJMP | 1001 0100 0001 1001 | PC ← EIND:Z. | 2 | avr6, XMEGA |
RCALL k | 1101 kkkk kkkk kkkk | Push PC + 1, then PC ← PC + k + 1. | 3 (4) | All |
CALL k | 1001 010k kkkk 111k + kkkk kkkk kkkk kkkk | Push PC + 2, then PC ← k. Two words. | 4 (5) | With JMP |
ICALL | 1001 0101 0000 1001 | Push PC + 1, then PC ← Z. | 3 (4) | All but avr1 |
EICALL | 1001 0101 0001 1001 | Push PC + 1, then PC ← EIND:Z. | 4 | avr6, XMEGA |
RET | 1001 0101 0000 1000 | Pop the return address into PC. | 4 (5) | All |
RETI | 1001 0101 0001 1000 | Pop the return address into PC and set the I flag. | 4 (5) | All |
The cycle count in brackets is for the three-byte return address.
Conditional branches
A conditional branch tests one bit of SREG and jumps −64 to +63 words from the next instruction. There are two encodings, BRBS s,k (branch if bit s is set,
1111 00kk kkkk ksss) and BRBC s,k (branch if clear, 1111 01kk kkkk ksss); every other name is one of them with s filled in. One cycle if not taken, two if taken.
| Bit s | Flag | BRBS written as | BRBC written as |
|---|---|---|---|
| 0 | C | BRCS / BRLO (lower, unsigned) | BRCC / BRSH (same or higher) |
| 1 | Z | BREQ (equal) | BRNE (not equal) |
| 2 | N | BRMI (minus) | BRPL (plus) |
| 3 | V | BRVS | BRVC |
| 4 | S | BRLT (less than, signed) | BRGE (greater or equal, signed) |
| 5 | H | BRHS | BRHC |
| 6 | T | BRTS | BRTC |
| 7 | I | BRIE (interrupt enabled) | BRID (disabled) |
The disassembler writes the names in the right-hand columns (brlo and brsh for bit 0, as llvm does) unless Aliases is off; then it writes
brbs 1, 0x0042. The target is shown as the absolute address.
Skips
A skip does not change the program counter itself: if its condition holds it makes the next instruction a no-op, so it lands after that instruction, whether that is one word or two (formats). One cycle if nothing is skipped, two if a one-word instruction is skipped, three if a two-word instruction is.
| Instruction | Encoding | Skips the next instruction if |
|---|---|---|
CPSE Rd,Rr | 0001 00rd dddd rrrr | Rd = Rr (no flags are changed). |
SBRC Rr,b | 1111 110r rrrr 0bbb | bit b of the register is clear. |
SBRS Rr,b | 1111 111r rrrr 0bbb | bit b of the register is set. |
SBIC A,b | 1001 1001 AAAA Abbb | bit b of I/O register A (0 to 31) is clear. |
SBIS A,b | 1001 1011 AAAA Abbb | bit b of I/O register A (0 to 31) is set. |
Not described
- Interrupt entry (the processor pushes the return address and jumps to a vector, with the I flag cleared): it is not an instruction.
- The cycle counts of
RET,RCALLand the others on XMEGA, tinyAVR 0/1/2 and the reduced core (they differ: the manual’s summary lists 2/3 cycles forRCALLon the XMEGA, 3 on the reduced core, and 6 forRETon it).