AVR Instruction Set – Arithmetic and logic

Add, subtract, compare, logic, multiply and DES

Reading the tables

Flags are written H S V N Z C (bits of SREG); a dash means the flag is not changed. Cycles are those of the classic cores (AVR, AVRe, AVRe+); the others differ (overview). Rd is the destination register, Rr the source; K a constant. “All” in the last column means every core has it.

Add, subtract, compare

InstructionEncodingOperationFlagsCyclesCores
ADD Rd,Rr0000 11rd dddd rrrrRd ← Rd + Rr. With Rd = Rr it is written LSL Rd.H S V N Z C1All
ADC Rd,Rr0001 11rd dddd rrrrRd ← Rd + Rr + C. With Rd = Rr it is written ROL Rd.H S V N Z C1All
ADIW Rd+1:Rd,K1001 0110 KKdd KKKKRd+1:Rd ← Rd+1:Rd + K (r24, r26, r28 or r30; K 0 to 63).S V N Z C2All but avr1 and the reduced core
SUB Rd,Rr0001 10rd dddd rrrrRd ← Rd − Rr.H S V N Z C1All
SUBI Rd,K0101 KKKK dddd KKKKRd ← Rd − K (r16 to r31).H S V N Z C1All
SBC Rd,Rr0000 10rd dddd rrrrRd ← Rd − Rr − C. Z stays clear if it was clear (for multi-byte compares).H S V N Z C1All
SBCI Rd,K0100 KKKK dddd KKKKRd ← Rd − K − C (r16 to r31).H S V N Z C1All
SBIW Rd+1:Rd,K1001 0111 KKdd KKKKRd+1:Rd ← Rd+1:Rd − K (r24, r26, r28 or r30; K 0 to 63).S V N Z C2All but avr1 and the reduced core
CP Rd,Rr0001 01rd dddd rrrrRd − Rr, the result discarded: sets the flags for a branch.H S V N Z C1All
CPC Rd,Rr0000 01rd dddd rrrrRd − Rr − C, discarded.H S V N Z C1All
CPI Rd,K0011 KKKK dddd KKKKRd − K, discarded (r16 to r31).H S V N Z C1All
NEG Rd1001 010d dddd 0001Rd ← 0 − Rd (two’s complement).H S V N Z C1All
INC Rd1001 010d dddd 0011Rd ← Rd + 1; C is not changed.S V N Z1All
DEC Rd1001 010d dddd 1010Rd ← Rd − 1; C is not changed.S V N Z1All

Logic

InstructionEncodingOperationFlagsCyclesCores
AND Rd,Rr0010 00rd dddd rrrrRd ← Rd AND Rr; V is cleared. With Rd = Rr it is written TST Rd.S V N Z1All
ANDI Rd,K0111 KKKK dddd KKKKRd ← Rd AND K (r16 to r31). Assemblers also write it CBR with the complement of the mask.S V N Z1All
OR Rd,Rr0010 10rd dddd rrrrRd ← Rd OR Rr.S V N Z1All
ORI Rd,K0110 KKKK dddd KKKKRd ← Rd OR K (r16 to r31). Assemblers also write it SBR.S V N Z1All
EOR Rd,Rr0010 01rd dddd rrrrRd ← Rd XOR Rr. With Rd = Rr it is written CLR Rd (Rd ← 0).S V N Z1All
COM Rd1001 010d dddd 0000Rd ← 0xFF − Rd (ones’ complement); C is set.S V N Z C1All

SER Rd (Rd ← 0xFF) is LDI Rd,0xFF: see LDI. The shifts and rotates are on the bits page.

Multiply

The hardware multiplier (cores avr4 and above, every XMEGA and the tinyAVR 0/1/2) leaves a 16-bit result in r1:r0, two cycles for every form. Only Z and C are changed: C is bit 15 of the result.

InstructionEncodingOperationCores
MUL Rd,Rr1001 11rd dddd rrrrr1:r0 ← Rd × Rr, both unsigned.avr4 and above
MULS Rd,Rr0000 0010 dddd rrrrr1:r0 ← Rd × Rr, both signed (r16 to r31).avr4 and above
MULSU Rd,Rr0000 0011 0ddd 0rrrr1:r0 ← Rd (signed) × Rr (unsigned); r16 to r23.avr4 and above
FMUL Rd,Rr0000 0011 0ddd 1rrrr1:r0 ← (Rd × Rr) << 1, fractional unsigned; r16 to r23.avr4 and above
FMULS Rd,Rr0000 0011 1ddd 0rrrr1:r0 ← (Rd × Rr) << 1, fractional signed.avr4 and above
FMULSU Rd,Rr0000 0011 1ddd 1rrrr1:r0 ← (Rd × Rr) << 1, Rd signed, Rr unsigned.avr4 and above

DES

InstructionEncodingOperationCyclesCores
DES K1001 0100 KKKK 1011One round of the Data Encryption Standard on the 64 bits in r7:r0 (data) and r15:r8 (key); K is the round number, 0 to 15. The half-carry flag H chooses the direction: clear encrypts, set decrypts.1 (2 when H is set)XMEGA only

Not described

  • The exact flag equations (the manual gives them); the decoder lists which flags change and which are read, both checked against a running core.
  • The two-cycle DES case when the half-carry flag is set is the manual’s statement; the decoder gives one cycle.