AVR Instruction Set: cores and devices

Two sets of names

Microchip’s manual names the cores by what they add: AVR (the original and classic instruction set), AVRe and AVRe+ (the enhanced core: MUL, MOVW, LPM Rd,Z, and JMP and CALL on the larger devices), AVRxm (XMEGA), AVRxt (the newer tinyAVR and megaAVR) and AVRrc (the reduced core). The compilers name the architectures (avr1 … avr6, avrxmega2 … avrxmega7, avrtiny), each of which is the set of instructions the devices of one range have, and a device belongs to one. The explorer offers the architecture names, and groups the XMEGA architectures (avrxmega2, 4, 5, 6 and 7 differ in memory size, not in instructions) as one choice. The Mode choice of the ELF viewer follows the e_flags of the file.

What each architecture has

Choice	e_flags	Core	RAM, LD/ST	`JMP` `CALL`	`IJMP` `ICALL`	`ADIW` `SBIW`	`MUL`	`MOVW`	`LPM` / `Rd,Z`	`ELPM`	`EIJMP`	`SPM`	`BREAK`	`DES`	`LAC` …
`avr1`	1	AVR	no	no	no	no	no	no	yes / no	no	no	no	no	no	no
`avr2`	2	AVR	yes	no	yes	yes	no	no	yes / no	no	no	no	no	no	no
`avr25`	25	AVRe	yes	no	yes	yes	no	yes	yes / yes	no	no	yes	yes	no	no
`avr3`	3	AVR	yes	yes	yes	yes	no	no	yes / no	no	no	no	no	no	no
`avr31`	31	AVR	yes	yes	yes	yes	no	no	yes / no	`ELPM` only	no	no	no	no	no
`avr35`	35	AVRe+	yes	yes	yes	yes	no	yes	yes / yes	no	no	yes	yes	no	no
`avr4`	4	AVRe+	yes	no	yes	yes	yes	yes	yes / yes	no	no	yes	yes	no	no
`avr5`	5	AVRe+	yes	yes	yes	yes	yes	yes	yes / yes	no	no	yes	yes	no	no
`avr51`	51	AVRe+	yes	yes	yes	yes	yes	yes	yes / yes	all forms	no	yes	yes	no	no
`avr6`	6	AVRe+	yes	yes	yes	yes	yes	yes	yes / yes	all forms	yes	yes	yes	no	no
`xmega`	102, 104 to 107	AVRxm	yes	yes	yes	yes	yes	yes	yes / yes	all forms	yes	yes (and `SPM Z+`)	yes	yes	yes
`xmega3`	103	AVRxt	yes	yes	yes	yes	yes	yes	yes / yes	no	no	no	yes	no	no
`avrtiny`	100	AVRrc	yes (one-word LDS/STS, no LDD)	no	no	no	no	no	no / no	no	no	no	yes	no	no

The table is the one llvm uses (its -mcpu names for these architectures are what the decoder is compared with), with the instructions the manual lists as not available on the reduced core (ADIW, SBIW, MUL, MOVW, LPM, ELPM, SPM, the XMEGA read-modify-write four, JMP, CALL, EIJMP, EICALL, DES, LDD, STD). The XMEGA’s LAC, LAS, LAT, XCH are in llvm’s rmw feature, which not every XMEGA device has; the decoder shows them for all XMEGA. avr1 is the AT90S1200 family and ATtiny11/12/15: the AT90S1200 itself has no LPM (llvm’s avr1 and ATtiny11 do).

What the choice changes in the viewer

An instruction that the core does not have is still decoded, with the status unavailable and a note that says which core has it.
The length of the skip instructions’ target (JMP and CALL are two words only on cores that have them).
The cycle counts: only the classic cores’ are tabulated, and avr6 adds the extra cycle for the three-byte return address.
On the reduced core the registers r0 to r15 are marked unavailable and LDS/STS are one word.

Not described

Individual devices: which architecture each of the several hundred has is in the compilers’ device lists.
The differences among the XMEGA architectures (memory size, RAMPX, RAMPY, RAMPD registers, the extra address byte of LD and ST on devices with more than 64 KB of data).

AVR Instruction Set – Cores and devices

Two sets of names

What each architecture has

What the choice changes in the viewer

Not described