65816 Instruction Set – Interrupt vectors

Where the processor looks for its handlers, in native and emulation mode

Introduction

The vectors are 16-bit addresses in bank 0 at the top of the address space. The processor reads one and continues in bank 0 (the program bank is cleared when it takes an interrupt in native mode). Native mode and emulation mode have separate sets.

The vectors

VectorNative modeEmulation modeTaken when
COP$FFE4$FFF4The COP instruction.
BRK$FFE6(the IRQ vector, $FFFE)The BRK instruction. In emulation mode it shares the IRQ vector; the B bit of the pushed status tells them apart.
ABORT$FFE8$FFF8The ABORT pin of the W65C816S. The Super Nintendo does not use it.
NMI$FFEA$FFFAA falling edge on the NMI pin. On the Super Nintendo: the start of the vertical blanking period, when enabled in $4200.
RESET(none)$FFFCA reset. The processor always starts in emulation mode, so there is only an emulation vector.
IRQ$FFEE$FFFEA low level on the IRQ pin when the I flag is clear. On the Super Nintendo: the H/V timer and the cartridge.

The bytes at $FFE0–$FFE3, $FFF0–$FFF3 and $FFF6–$FFF7 are not vectors.

What happens

  • Native mode: the processor pushes the program bank, the program counter (high byte first) and the status register, sets I, clears D and loads the program counter from the vector, in bank 0. The handler ends with rti, which pulls them in reverse. M and X are not changed on entry.
  • Emulation mode: as above without the program bank (3 bytes pushed). The pushed status has bit 4 set for BRK and clear for the others.
  • Reset: the registers are not defined, except that E is 1, M and X are 1, D is cleared, I is set, the stack pointer’s high byte is 1 and the program bank and direct page register are zero.

On the Super Nintendo

The cartridge supplies the vectors: they are the last 32 bytes of the first ROM bank, at $FFE0–$FFFF of bank 0, which is also the end of the cartridge’s internal header. The internal header page lists them, and the explorer’s SNES viewer shows them with the instruction each points to.

Not described

Known, not yet covered

  • Reference: the cycle-by-cycle order of the pushes and the vector fetch, and when the processor samples the interrupt inputs.

Unknown

  • Reference: the register contents after a power-on reset other than those listed; the data sheet leaves them undefined.

Links

Reference