Introduction
The high nibble of the opcode is the row, the low nibble the column. Every cell is a defined instruction; there are no undocumented opcodes. In the cells:
#is an immediate operand. A cell marked M is 1 byte of operand when the M flag is set and 2 when it is clear; one marked X follows the X flag (the M and X flags). All other cells have one length.dpdirect page,absabsolute,long24-bit,sr,Sstack relative,(…)indirect,[…]indirect long,relandrell8-bit and 16-bit relative,src,dsta block move (addressing modes).- The cell of
wdm(42) is the only reserved opcode.
The map
| x0 | x1 | x2 | x3 | x4 | x5 | x6 | x7 | x8 | x9 | xA | xB | xC | xD | xE | xF | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x | BRK # | ORA (dp,X) | COP # | ORA sr,S | TSB dp | ORA dp | ASL dp | ORA [dp] | PHP | ORA #M | ASL A | PHD | TSB abs | ORA abs | ASL abs | ORA long |
| 1x | BPL rel | ORA (dp),Y | ORA (dp) | ORA (sr,S),Y | TRB dp | ORA dp,X | ASL dp,X | ORA [dp],Y | CLC | ORA abs,Y | INC A | TCS | TRB abs | ORA abs,X | ASL abs,X | ORA long,X |
| 2x | JSR abs | AND (dp,X) | JSL long | AND sr,S | BIT dp | AND dp | ROL dp | AND [dp] | PLP | AND #M | ROL A | PLD | BIT abs | AND abs | ROL abs | AND long |
| 3x | BMI rel | AND (dp),Y | AND (dp) | AND (sr,S),Y | BIT dp,X | AND dp,X | ROL dp,X | AND [dp],Y | SEC | AND abs,Y | DEC A | TSC | BIT abs,X | AND abs,X | ROL abs,X | AND long,X |
| 4x | RTI | EOR (dp,X) | WDM # | EOR sr,S | MVP src,dst | EOR dp | LSR dp | EOR [dp] | PHA | EOR #M | LSR A | PHK | JMP abs | EOR abs | LSR abs | EOR long |
| 5x | BVC rel | EOR (dp),Y | EOR (dp) | EOR (sr,S),Y | MVN src,dst | EOR dp,X | LSR dp,X | EOR [dp],Y | CLI | EOR abs,Y | PHY | TCD | JML long | EOR abs,X | LSR abs,X | EOR long,X |
| 6x | RTS | ADC (dp,X) | PER rell | ADC sr,S | STZ dp | ADC dp | ROR dp | ADC [dp] | PLA | ADC #M | ROR A | RTL | JMP (abs) | ADC abs | ROR abs | ADC long |
| 7x | BVS rel | ADC (dp),Y | ADC (dp) | ADC (sr,S),Y | STZ dp,X | ADC dp,X | ROR dp,X | ADC [dp],Y | SEI | ADC abs,Y | PLY | TDC | JMP (abs,X) | ADC abs,X | ROR abs,X | ADC long,X |
| 8x | BRA rel | STA (dp,X) | BRL rell | STA sr,S | STY dp | STA dp | STX dp | STA [dp] | DEY | BIT #M | TXA | PHB | STY abs | STA abs | STX abs | STA long |
| 9x | BCC rel | STA (dp),Y | STA (dp) | STA (sr,S),Y | STY dp,X | STA dp,X | STX dp,Y | STA [dp],Y | TYA | STA abs,Y | TXS | TXY | STZ abs | STA abs,X | STZ abs,X | STA long,X |
| Ax | LDY #X | LDA (dp,X) | LDX #X | LDA sr,S | LDY dp | LDA dp | LDX dp | LDA [dp] | TAY | LDA #M | TAX | PLB | LDY abs | LDA abs | LDX abs | LDA long |
| Bx | BCS rel | LDA (dp),Y | LDA (dp) | LDA (sr,S),Y | LDY dp,X | LDA dp,X | LDX dp,Y | LDA [dp],Y | CLV | LDA abs,Y | TSX | TYX | LDY abs,X | LDA abs,X | LDX abs,Y | LDA long,X |
| Cx | CPY #X | CMP (dp,X) | REP # | CMP sr,S | CPY dp | CMP dp | DEC dp | CMP [dp] | INY | CMP #M | DEX | WAI | CPY abs | CMP abs | DEC abs | CMP long |
| Dx | BNE rel | CMP (dp),Y | CMP (dp) | CMP (sr,S),Y | PEI (dp) | CMP dp,X | DEC dp,X | CMP [dp],Y | CLD | CMP abs,Y | PHX | STP | JML [abs] | CMP abs,X | DEC abs,X | CMP long,X |
| Ex | CPX #X | SBC (dp,X) | SEP # | SBC sr,S | CPX dp | SBC dp | INC dp | SBC [dp] | INX | SBC #M | NOP | XBA | CPX abs | SBC abs | INC abs | SBC long |
| Fx | BEQ rel | SBC (dp),Y | SBC (dp) | SBC (sr,S),Y | PEA abs | SBC dp,X | INC dp,X | SBC [dp],Y | SED | SBC abs,Y | PLX | XCE | JSR (abs,X) | SBC abs,X | INC abs,X | SBC long,X |
Not described
Known, not yet covered
- Reference: the byte count and cycle count of each cell are on the instruction pages (data transfer, arithmetic, logic, control transfer, flags and other), not in this table.
Links
Reference
- 65816 reference – the Super Famicom Development Wiki’s instruction table
- W65C816S data sheet – Western Design Center: the opcode matrix