65816 Instruction Set – Logic, shifts and bit tests

AND, ORA, EOR, BIT, the shifts and rotates, TSB and TRB

Introduction

The logic instructions work on the accumulator, 8 or 16 bits by M. The shifts and rotates work on the accumulator or on memory, and, as the 65C02 does, BIT has an immediate form and TSB and TRB set and clear bits in memory.

The instructions

Each form is written mode opcode, bytes, cycles, then the cycle tags.

InstructionFormsWhat it doesFlags
andimm 29, 2 or 3, 2 +M
dp 25, 2, 3 +M +DL
dp,X 35, 2, 4 +M +DL
abs 2D, 3, 4 +M
abs,X 3D, 3, 4 +M +P
abs,Y 39, 3, 4 +M +P
long 2F, 4, 5 +M
long,X 3F, 4, 5 +M
(dp) 32, 2, 5 +M +DL
(dp,X) 21, 2, 6 +M +DL
(dp),Y 31, 2, 5 +M +DL +P
[dp] 27, 2, 6 +M +DL
[dp],Y 37, 2, 6 +M +DL
sr,S 23, 2, 4 +M
(sr,S),Y 33, 2, 7 +M		A = A AND memory.N Z
oraimm 09, 2 or 3, 2 +M
dp 05, 2, 3 +M +DL
dp,X 15, 2, 4 +M +DL
abs 0D, 3, 4 +M
abs,X 1D, 3, 4 +M +P
abs,Y 19, 3, 4 +M +P
long 0F, 4, 5 +M
long,X 1F, 4, 5 +M
(dp) 12, 2, 5 +M +DL
(dp,X) 01, 2, 6 +M +DL
(dp),Y 11, 2, 5 +M +DL +P
[dp] 07, 2, 6 +M +DL
[dp],Y 17, 2, 6 +M +DL
sr,S 03, 2, 4 +M
(sr,S),Y 13, 2, 7 +M		A = A OR memory.N Z
eorimm 49, 2 or 3, 2 +M
dp 45, 2, 3 +M +DL
dp,X 55, 2, 4 +M +DL
abs 4D, 3, 4 +M
abs,X 5D, 3, 4 +M +P
abs,Y 59, 3, 4 +M +P
long 4F, 4, 5 +M
long,X 5F, 4, 5 +M
(dp) 52, 2, 5 +M +DL
(dp,X) 41, 2, 6 +M +DL
(dp),Y 51, 2, 5 +M +DL +P
[dp] 47, 2, 6 +M +DL
[dp],Y 57, 2, 6 +M +DL
sr,S 43, 2, 4 +M
(sr,S),Y 53, 2, 7 +M		A = A exclusive-OR memory.N Z
bitimm 89, 2 or 3, 2 +M
dp 24, 2, 3 +M +DL
dp,X 34, 2, 4 +M +DL
abs 2C, 3, 4 +M
abs,X 3C, 3, 4 +M +P		Z is set when A AND memory is zero. With a memory operand N and V become the top two bits of the memory value (bits 7 and 6, or 15 and 14); the immediate form changes only Z.N V Z (imm: Z)
aslacc 0A, 1, 2
dp 06, 2, 5 +2M +DL
dp,X 16, 2, 6 +2M +DL
abs 0E, 3, 6 +2M
abs,X 1E, 3, 7 +2M		Shift left; bit 0 becomes 0 and the top bit goes to C.N Z C
lsracc 4A, 1, 2
dp 46, 2, 5 +2M +DL
dp,X 56, 2, 6 +2M +DL
abs 4E, 3, 6 +2M
abs,X 5E, 3, 7 +2M		Shift right; the top bit becomes 0 and bit 0 goes to C.N Z C
rolacc 2A, 1, 2
dp 26, 2, 5 +2M +DL
dp,X 36, 2, 6 +2M +DL
abs 2E, 3, 6 +2M
abs,X 3E, 3, 7 +2M		Rotate left through carry.N Z C
roracc 6A, 1, 2
dp 66, 2, 5 +2M +DL
dp,X 76, 2, 6 +2M +DL
abs 6E, 3, 6 +2M
abs,X 7E, 3, 7 +2M		Rotate right through carry.N Z C
tsbdp 04, 2, 5 +2M +DL
abs 0C, 3, 6 +2M		Test and set bits: Z is set when A AND memory is zero; then memory = memory OR A.Z
trbdp 14, 2, 5 +2M +DL
abs 1C, 3, 6 +2M		Test and reset bits: Z as TSB; then memory = memory AND NOT A.Z

Not described

Known, not yet covered

  • Reference: the bus cycles of each instruction (the read, write and dummy cycles of a read-modify-write), as on the overview.

Links

Reference