65816 Instruction Set: Arithmetic and comparison

Introduction

The 65816 adds and subtracts with the carry flag as the 6502 does, but on 8 or 16 bits at a time, by M: a 16-bit addition needs one clc and one adc. There is still no multiply or divide in the processor (the Super Nintendo has them as registers beside it). Comparisons set carry as a subtraction does and keep no result.

The instructions

Each form is written mode opcode, bytes, cycles, then the cycle tags; “2 or 3” bytes is the immediate form, 3 when the flag after the tag is clear.

Instruction	Forms	What it does	Flags
`adc`	imm `69`, 2 or 3, 2 +M dp `65`, 2, 3 +M +DL dp,X `75`, 2, 4 +M +DL abs `6D`, 3, 4 +M abs,X `7D`, 3, 4 +M +P abs,Y `79`, 3, 4 +M +P long `6F`, 4, 5 +M long,X `7F`, 4, 5 +M (dp) `72`, 2, 5 +M +DL (dp,X) `61`, 2, 6 +M +DL (dp),Y `71`, 2, 5 +M +DL +P [dp] `67`, 2, 6 +M +DL [dp],Y `77`, 2, 6 +M +DL sr,S `63`, 2, 4 +M (sr,S),Y `73`, 2, 7 +M	A = A + memory + C, on 8 or 16 bits. See decimal mode.	N V Z C
`sbc`	imm `E9`, 2 or 3, 2 +M dp `E5`, 2, 3 +M +DL dp,X `F5`, 2, 4 +M +DL abs `ED`, 3, 4 +M abs,X `FD`, 3, 4 +M +P abs,Y `F9`, 3, 4 +M +P long `EF`, 4, 5 +M long,X `FF`, 4, 5 +M (dp) `F2`, 2, 5 +M +DL (dp,X) `E1`, 2, 6 +M +DL (dp),Y `F1`, 2, 5 +M +DL +P [dp] `E7`, 2, 6 +M +DL [dp],Y `F7`, 2, 6 +M +DL sr,S `E3`, 2, 4 +M (sr,S),Y `F3`, 2, 7 +M	A = A − memory − (1 − C): the carry is the inverse of the borrow.	N V Z C
`cmp`	imm `C9`, 2 or 3, 2 +M dp `C5`, 2, 3 +M +DL dp,X `D5`, 2, 4 +M +DL abs `CD`, 3, 4 +M abs,X `DD`, 3, 4 +M +P abs,Y `D9`, 3, 4 +M +P long `CF`, 4, 5 +M long,X `DF`, 4, 5 +M (dp) `D2`, 2, 5 +M +DL (dp,X) `C1`, 2, 6 +M +DL (dp),Y `D1`, 2, 5 +M +DL +P [dp] `C7`, 2, 6 +M +DL [dp],Y `D7`, 2, 6 +M +DL sr,S `C3`, 2, 4 +M (sr,S),Y `D3`, 2, 7 +M	Compares A with memory (A − memory, result discarded): C is set when A is at least the memory (unsigned), Z when they are equal.	N Z C
`cpx`	imm `E0`, 2 or 3, 2 +X dp `E4`, 2, 3 +X +DL abs `EC`, 3, 4 +X	Compares X with memory.	N Z C
`cpy`	imm `C0`, 2 or 3, 2 +X dp `C4`, 2, 3 +X +DL abs `CC`, 3, 4 +X	Compares Y with memory.	N Z C
`inc`	acc `1A`, 1, 2 dp `E6`, 2, 5 +2M +DL dp,X `F6`, 2, 6 +2M +DL abs `EE`, 3, 6 +2M abs,X `FE`, 3, 7 +2M	Adds one to A or to memory (8 or 16 bits by M). The accumulator form is also written `ina`.	N Z
`dec`	acc `3A`, 1, 2 dp `C6`, 2, 5 +2M +DL dp,X `D6`, 2, 6 +2M +DL abs `CE`, 3, 6 +2M abs,X `DE`, 3, 7 +2M	Subtracts one. The accumulator form is also written `dea`.	N Z
`inx`	imp `E8`, 1, 2	X = X + 1 (8 or 16 bits by X).	N Z
`iny`	imp `C8`, 1, 2	Y = Y + 1.	N Z
`dex`	imp `CA`, 1, 2	X = X − 1.	N Z
`dey`	imp `88`, 1, 2	Y = Y − 1.	N Z

Decimal mode

When the D flag is set, ADC and SBC treat each four bits as a decimal digit, so a 16-bit operation handles four digits. N, V and Z are valid in decimal mode, as on the 65C02. The cycle notes of the Super Famicom Development Wiki list no extra cycle for it (the 65C02’s data sheet has one), and the LakeSnes core the explorer was checked against adds none. The Super Nintendo’s 5A22 has decimal mode.

Notes

Overflow. V is set when two numbers of the same sign give a result of the other sign, for signed arithmetic, at the width of the operation.
Memory increments are read-modify-write: a 16-bit one reads and writes two bytes, which the +2M tag counts. This matters when the address is a hardware register.

Not described

Known, not yet covered

Reference: whether decimal mode takes an extra cycle on the 65816. The sources read for this page list none (the 65C02’s data sheet does), and the explorer gives the base count; the WDC data sheet itself was not read in full.

65816 Instruction Set – Arithmetic and comparison