How it differs from the Z80
The Sharp SM83 (the LR35902 in some sources) is in the Game Boy and the Game Boy Color. Its encoding looks like the Z80’s, but it is another processor:
- No
IX,IY, shadow registers,I,R, I/O instructions (IN,OUT) or block instructions. NoED,DDorFDprefixes: those opcodes are not instructions.CBremains. - The flag register has four flags in the high nibble:
Z(bit 7),N(6),H(5),C(4). The low four bits always read as 0. There are no S, P/V, X or Y flags. - Added:
LDH(load from and to$FF00+n),LD (C),AandLD A,(C)(the address is$FF00+C),LD (HL+),Aand its three relatives,LD (nn),SP,ADD SP,d,LD HL,SP+d,SWAP(in place ofSLL),STOP. RLCA,RRCA,RLA,RRAclearZ; on the Z80 they leave it alone.RETIis a plain opcode ($D9);JP (HL)is writtenJP HL.- Eleven opcodes are not defined and lock the processor: the viewer shows them with the status jam and the name
invalid:D3 DB DD E3 E4 EB EC ED F4 FC FD.
T-states below are clock cycles (four per machine cycle) at the console’s normal speed. The Game Boy Color can switch to double speed; the counts then take half the time.
Instructions
Operands as on the Z80 page; d is a signed 8-bit number, n an 8-bit number, nn 16 bits. Flags are the ones changed; 0 or 1 after a flag means it is set to that value.
| Mnemonic | Forms | Bytes | T | Flags | What it does |
|---|---|---|---|---|---|
NOP | 1 | 4 | none | Do nothing. | |
STOP | 10 00 | 2 | 4 | none | Stop the processor and the LCD until a button is pressed. On a Game Boy Color with the speed switch armed in KEY1 ($FF4D) it changes speed. The second byte should be 00. |
HALT | 1 | 4 | none | Wait for an interrupt. If interrupts are off but one is pending the next byte is read twice (the “HALT bug”). | |
LD | r,r' · r,n · r,(HL) · (HL),r · (HL),n · A,(BC) · A,(DE) · (BC),A · (DE),A · (HL+),A · (HL-),A · A,(HL+) · A,(HL-) · rr,nn · (nn),SP · (nn),A · A,(nn) · (C),A · A,(C) · SP,HL · HL,SP+d | 1–3 | 4 (r,r) · 8 (r,n; with a pointer) · 12 (rr,nn; (HL),n; HL,SP+d) · 16 ((nn),A; A,(nn)) · 20 ((nn),SP) · 8 (SP,HL) | none; HL,SP+d: Z0 N0 H C | Copy. HL+ and HL- add or subtract 1 from HL after the access. HL,SP+d sets H and C from the carry out of bits 3 and 7 of the low byte of SP+d. |
LDH | (n),A · A,(n) | 2 | 12 | none | Store or load the byte at $FF00 + n (hardware registers and HRAM). |
PUSH | BC DE HL AF | 1 | 16 | none | Push a pair. |
POP | BC DE HL AF | 1 | 12 | Z N H C for AF | Pull a pair (the low nibble of F becomes 0). |
ADD | A,r · A,n · HL,rr · SP,d | 1–2 | 4 · 8 · 8 (HL,rr) · 16 (SP,d) | Z N H C; HL,rr: N0 H C (Z kept); SP,d: Z0 N0 H C | Add. |
ADC | A,r · A,n | 1–2 | 4 · 8 | Z N H C | Add with carry. |
SUB | r · n | 1–2 | 4 · 8 | Z N H C | Subtract. |
SBC | A,r · A,n | 1–2 | 4 · 8 | Z N H C | Subtract with carry. |
AND | r · n | 1–2 | 4 · 8 | Z N0 H1 C0 | AND with A. |
XOR | r · n | 1–2 | 4 · 8 | Z N0 H0 C0 | Exclusive OR with A. |
OR | r · n | 1–2 | 4 · 8 | Z N0 H0 C0 | OR with A. |
CP | r · n | 1–2 | 4 · 8 | Z N1 H C | Compare with A. |
INC | r · (HL) · rr | 1 | 4 · 12 · 8 | Z N0 H (none for rr) | Add 1. |
DEC | r · (HL) · rr | 1 | 4 · 12 · 8 | Z N1 H (none for rr) | Subtract 1. |
DAA | 1 | 4 | Z H0 C | Decimal adjust A. | |
CPL | 1 | 4 | N1 H1 | Complement A. | |
SCF | 1 | 4 | N0 H0 C1 | Set carry. | |
CCF | 1 | 4 | N0 H0 C | Complement carry. | |
DI | 1 | 4 | none | Disable interrupts (clear IME). | |
EI | 1 | 4 | none | Enable interrupts after the next instruction. | |
RLCA | 1 | 4 | Z0 N0 H0 C | Rotate A left. | |
RRCA | 1 | 4 | Z0 N0 H0 C | Rotate A right. | |
RLA | 1 | 4 | Z0 N0 H0 C | Rotate A left through carry. | |
RRA | 1 | 4 | Z0 N0 H0 C | Rotate A right through carry. | |
RLC | r · (HL) (CB) | 2 | 8 · 16 | Z N0 H0 C | Rotate left. |
RRC | as RLC | 2 | 8 · 16 | Z N0 H0 C | Rotate right. |
RL | as RLC | 2 | 8 · 16 | Z N0 H0 C | Rotate left through carry. |
RR | as RLC | 2 | 8 · 16 | Z N0 H0 C | Rotate right through carry. |
SLA | as RLC | 2 | 8 · 16 | Z N0 H0 C | Shift left. |
SRA | as RLC | 2 | 8 · 16 | Z N0 H0 C | Shift right keeping bit 7. |
SWAP | as RLC (CB 30–37) | 2 | 8 · 16 | Z N0 H0 C0 | Exchange the two nibbles. |
SRL | as RLC | 2 | 8 · 16 | Z N0 H0 C | Shift right; bit 7 becomes 0. |
BIT | b,r · b,(HL) | 2 | 8 · 12 | Z N0 H1 | Test bit b. |
RES | b,r · b,(HL) | 2 | 8 · 16 | none | Clear bit b. |
SET | b,r · b,(HL) | 2 | 8 · 16 | none | Set bit b. |
JP | nn · cc,nn · HL | 3 (1) | 16 · 12 / 16 · 4 | none | Jump. Conditions NZ Z NC C only. JP HL jumps to the address in HL. |
JR | d · cc,d | 2 | 12 · 8 / 12 | none | Jump relative to the next instruction. |
CALL | nn · cc,nn | 3 | 24 · 12 / 24 | none | Push the return address, then jump. |
RET | · · cc | 1 | 16 · 8 / 20 | none | Return. |
RETI | 1 | 16 | none | Return and enable interrupts. | |
RST | $00 $08 … $38 | 1 | 16 | none | Call the fixed address. |
invalid | D3 DB DD E3 E4 EB EC ED F4 FC FD | 1 | locks up | none | Not an instruction: the processor locks up until reset. Status jam. |
Opcode map
X is one of the 11 invalid opcodes. The $40–$BF blocks are as on the Z80: $40 + 8·dst + src is LD dst,src ($76 is HALT) and
$80 + 8·op + src the arithmetic group, both over the registers B C D E H L (HL) A.
| x0 | x1 | x2 | x3 | x4 | x5 | x6 | x7 | x8 | x9 | xA | xB | xC | xD | xE | xF | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x | nop | ld bc,nn | ld (bc),a | inc bc | inc b | dec b | ld b,n | rlca | ld (nn),sp | add hl,bc | ld a,(bc) | dec bc | inc c | dec c | ld c,n | rrca |
| 1x | stop n | ld de,nn | ld (de),a | inc de | inc d | dec d | ld d,n | rla | jr d | add hl,de | ld a,(de) | dec de | inc e | dec e | ld e,n | rra |
| 2x | jr nz,d | ld hl,nn | ld (hl+),a | inc hl | inc h | dec h | ld h,n | daa | jr z,d | add hl,hl | ld a,(hl+) | dec hl | inc l | dec l | ld l,n | cpl |
| 3x | jr nc,d | ld sp,nn | ld (hl-),a | inc sp | inc (hl) | dec (hl) | ld (hl),n | scf | jr c,d | add hl,sp | ld a,(hl-) | dec sp | inc a | dec a | ld a,n | ccf |
| Cx | ret nz | pop bc | jp nz,nn | jp nn | call nz,nn | push bc | add a,n | rst $00 | ret z | ret | jp z,nn | CB | call z,nn | call nn | adc a,n | rst $08 |
| Dx | ret nc | pop de | jp nc,nn | X | call nc,nn | push de | sub n | rst $10 | ret c | reti | jp c,nn | X | call c,nn | X | sbc a,n | rst $18 |
| Ex | ldh (n),a | pop hl | ld (c),a | X | X | push hl | and n | rst $20 | add sp,d | jp hl | ld (nn),a | X | X | X | xor n | rst $28 |
| Fx | ldh a,(n) | pop af | ld a,(c) | di | X | push af | or n | rst $30 | ld hl,sp+d | ld sp,hl | ld a,(nn) | ei | X | X | cp n | rst $38 |
CB page: by bits 5–3 RLC RRC RL RR SLA SRA SWAP SRL for $00–$3F, then BIT, RES, SET with the bit number in bits 5–3, on the register in bits 2–0.
How this was checked
All 256 opcodes and the 256 CB opcodes were compared with a grid written separately from Pan Docs, and each defined opcode was run on the Game Boy core of
GameBoy-Online (GameBoyCore.js) from several states: length, registers and flags changed and read, memory touched and T-states agreed for all 493 defined opcodes tried
(STOP, HALT, DI and EI are not run). That core knows the camera cartridge by the code $1F; Pan Docs says $FC.
Sources
- CPU Instruction Set – Pan Docs
- CPU comparison with the Z80 – Pan Docs
Not described
Interrupt timing, the HALT bug in detail, the double-speed mode’s effect on the other hardware, and the instruction timing inside a machine cycle.