Z80 Instruction Set – eZ80

What the eZ80 is

The eZ80 runs Z80 programs and adds a 24-bit address space (16 MiB), 24-bit registers, a hardware multiplier and a set of new instructions. It is found in the Agon Light and the TI-84 Plus CE. The Z80 instructions are as on the Z80 page; this page lists only what differs.

ADL mode and Z80 mode

The processor is in one of two modes, held in the ADL bit. In ADL mode addresses and the 16-bit registers BC DE HL IX IY SP are 24 bits wide; a 16-bit number in an instruction (nn) becomes 24 bits, and the stack holds three bytes per pushed pair. In Z80 mode they are 16 bits and the address is completed from the MBASE register. A program switches between the modes with jumps, calls and returns that carry a suffix (STMIX and RSMIX set and clear the separate MADL flag), so the bytes alone do not say which mode a piece of code runs in.

This matters because the length of an instruction depends on the mode. LD HL,nn is 3 bytes in Z80 mode and 4 in ADL mode. The explorer cannot tell, so its eZ80 disassembly has an option, Mode, with the choices ADL mode and Z80 mode. It decodes every byte as an instruction start, so you can see how the code reads in each mode.

Suffix opcodes

Four opcodes that do nothing on a Z80 (LD B,B, LD C,C, LD D,D, LD E,E) are on the eZ80 prefixes that override the mode for one instruction. The first letter is the size of the instruction’s own addressing (the stack and pointer width), the second the size of the immediate address or data:

The suffix and the instruction after it are one instruction: the viewer writes it as ld.lil hl,$123456. A short instruction jumps within the MBASE segment: the viewer shows the 24-bit immediate as written and takes the low 16 bits as the target. The Agon core agrees on the length of every suffixed instruction tried; for a CALL.SIL it goes to the full 24-bit address, where JP.SIL uses the low 16 bits.

Added instructions

All are in the ED page (some in DD and FD). The eZ80 gives the Z80’s repeated ED opcodes new meanings, so the Z80’s “undocumented duplicates” of NEG, RETN and IM do not all exist on the eZ80.

Every instruction’s mnemonics are cross-checked in the assembler test list of GNU binutils (see sources); the encodings above were checked by running them on the Agon core.

What the real core says

Each opcode sequence, in both modes and behind each suffix, was run on the eZ80 core of the Agon Light emulator (5,228 combinations of opcode sequence and mode). The length agrees with the decoder for 5,201 of the 5,204 documented sequences. Differences found:

• TSTIO n: the manual gives three bytes (ED 74 n); the core takes two.
• The core also runs ED 0A 0B 1A 1B 2A 2B 3A 3B as three-byte LEAs (the same as 02 03 12 13 22 23 32 33). The manual lists only one encoding of each; the viewer follows the manual and shows these as two-byte no-ops.
• CALL.SIL goes to the full 24-bit address in the core, where JP.SIL uses the low 16 bits.
• In the undocumented DD CB d op register copies the core applies the prefix to H and L (it writes IXH or IXL).
• A DD or FD before a suffix opcode is taken by the core as one prefixed instruction; the viewer shows the DD alone.

Sources

• eZ80 CPU User Manual (UM0077) – Zilog
• ez80_adl_all.s – GNU binutils assembler test, the list of eZ80 mnemonics
• TSTIO n – eZ80 user manual page

Not described

• Cycle counts: the explorer does not show them for the eZ80.
• The undocumented Z80 opcodes on the eZ80 (IXH and IXL, SLL, the DDCB register copies, ED duplicates): they are decoded as on the Z80 and marked undocumented, but whether the eZ80 hardware runs them is not checked.
• The encodings of the block I/O additions come from memory of the manual and the Agon core only; they have not been re-read against the printed table.
• Following the mode through the program (the viewer does not track STMIX, RSMIX or suffixed calls: you choose the mode).