The 8080
The Intel 8080 (1974) has registers A B C D E H L, SP, PC and the five flags S Z H P C
(H is the auxiliary carry). The Z80 runs 8080 programs, but spells every instruction differently, so an 8080 listing is hard to read for a Z80 programmer: MOV B,C is
LD B,C; JMP is JP; M stands for the byte at (HL); B, D, H and SP name the pairs
BC, DE, HL and SP, and PSW is AF. The 8080 has 244 defined opcodes, no prefixes, and instructions of 1 to 3 bytes. T-states are the 8080’s (the 8085’s differ and are not listed).
An instruction with a condition has two counts: not taken / taken.
Condition suffixes: NZ Z NC C PO PE P M. Operand letters: r a register B C D E H L M A; rp a pair B D H SP; n 8 bits; nn 16 bits.
Instructions
| Mnemonic | Forms | Bytes | T | Flags | What it does (Z80 spelling) |
|---|---|---|---|---|---|
NOP | 1 | 4 | none | NOP | |
MOV | r,r' | 1 | 5 (7 with M) | none | LD r,r' |
MVI | r,n | 2 | 7 (10 with M) | none | LD r,n |
LXI | rp,nn | 3 | 10 | none | LD rr,nn |
LDA | nn | 3 | 13 | none | LD A,(nn) |
STA | nn | 3 | 13 | none | LD (nn),A |
LHLD | nn | 3 | 16 | none | LD HL,(nn) |
SHLD | nn | 3 | 16 | none | LD (nn),HL |
LDAX | B · D | 1 | 7 | none | LD A,(BC) / (DE) |
STAX | B · D | 1 | 7 | none | LD (BC),A / (DE),A |
XCHG | 1 | 4 | none | EX DE,HL | |
ADD | r | 1 | 4 (7 with M) | S Z H P C | ADD A,r |
ADC | r | 1 | 4 (7) | S Z H P C | ADC A,r |
SUB | r | 1 | 4 (7) | S Z H P C | SUB r |
SBB | r | 1 | 4 (7) | S Z H P C | SBC A,r |
ANA | r | 1 | 4 (7) | S Z H P C | AND r |
XRA | r | 1 | 4 (7) | S Z H P C | XOR r |
ORA | r | 1 | 4 (7) | S Z H P C | OR r |
CMP | r | 1 | 4 (7) | S Z H P C | CP r |
ADI | n | 2 | 7 | S Z H P C | ADD A,n |
ACI | n | 2 | 7 | S Z H P C | ADC A,n |
SUI | n | 2 | 7 | S Z H P C | SUB n |
SBI | n | 2 | 7 | S Z H P C | SBC A,n |
ANI | n | 2 | 7 | S Z H P C | AND n |
XRI | n | 2 | 7 | S Z H P C | XOR n |
ORI | n | 2 | 7 | S Z H P C | OR n |
CPI | n | 2 | 7 | S Z H P C | CP n (not the Z80’s block compare) |
INR | r | 1 | 5 (10 with M) | S Z H P | INC r |
DCR | r | 1 | 5 (10) | S Z H P | DEC r |
INX | rp | 1 | 5 | none | INC rr |
DCX | rp | 1 | 5 | none | DEC rr |
DAD | rp | 1 | 10 | C | ADD HL,rr |
DAA | 1 | 4 | S Z H P C | DAA | |
RLC | 1 | 4 | C | RLCA | |
RRC | 1 | 4 | C | RRCA | |
RAL | 1 | 4 | C | RLA | |
RAR | 1 | 4 | C | RRA | |
CMA | 1 | 4 | none | CPL | |
STC | 1 | 4 | C | SCF | |
CMC | 1 | 4 | C | CCF | |
JMP | nn | 3 | 10 | none | JP nn |
Jcc | JNZ JZ JNC JC JPO JPE JP JM nn | 3 | 10 (both ways) | none | JP cc,nn (JP here is “jump if plus”) |
PCHL | 1 | 5 | none | JP (HL) | |
CALL | nn | 3 | 17 | none | CALL nn |
Ccc | CNZ CZ CNC CC CPO CPE CP CM nn | 3 | 11 / 17 | none | CALL cc,nn |
RET | 1 | 10 | none | RET | |
Rcc | RNZ RZ RNC RC RPO RPE RP RM | 1 | 5 / 11 | none | RET cc |
RST | 0 … 7 | 1 | 11 | none | RST 8·n |
PUSH | B D H PSW | 1 | 11 | none | PUSH rr |
POP | B D H PSW | 1 | 10 | S Z H P C for PSW | POP rr |
XTHL | 1 | 18 | none | EX (SP),HL | |
SPHL | 1 | 5 | none | LD SP,HL | |
IN | n | 2 | 10 | none | IN A,(n) |
OUT | n | 2 | 10 | none | OUT (n),A |
EI | 1 | 4 | none | EI | |
DI | 1 | 4 | none | DI | |
HLT | 1 | 7 | none | HALT |
Undocumented 8080 opcodes
Twelve opcodes are not in Intel’s manual. The viewer marks them undocumented:
| Opcodes | Act as |
|---|---|
08 10 18 20 28 30 38 | NOP |
CB | JMP nn |
D9 | RET |
DD ED FD | CALL nn |
On the Z80 and the SM83 these bytes are other things (prefixes, EXX, RETI).
The 8085
The Intel 8085 runs the 8080’s instruction set and adds two documented instructions in place of two of the 8080’s undocumented NOPs: RIM (20, read the interrupt masks and the serial input bit into A) and
SIM (30, set the interrupt masks and serial output from A). Its own undocumented opcodes are decoded as follows; their names are those the 8085’s assemblers use, and they are marked undocumented. T-states are not listed for the 8085.
| Opcode | Mnemonic | What it does |
|---|---|---|
08 | DSUB | HL = HL − BC |
10 | ARHL | Shift HL right one bit, keeping the sign |
18 | RDEL | Rotate DE left through carry |
28 n | LDHI n | DE = HL + n |
38 n | LDSI n | DE = SP + n |
CB | RSTV | Call $0040 if the overflow flag is set |
D9 | SHLX | Store HL at the address in DE |
ED | LHLX | Load HL from the address in DE |
DD nn | JNK nn (JNX5) | Jump if the K flag (X5) is clear |
FD nn | JK nn (JX5) | Jump if the K flag is set |
How this was checked
All 256 opcodes of both processors were compared with a grid written separately from Intel’s opcode table. Operand text, length and the documented or undocumented state agree for every opcode. The 8080 was not run on a core, and the instruction effects (registers and flags read and written) of the 8080 decoder were not checked against one; the 8085’s undocumented instructions were written from memory of published descriptions and are not checked against a source.
Sources
- Intel, 8080 Assembly Language Programming Manual – the instruction set and timing (the opcode grid used for the checks was written from memory of it; no copy was read for this page)
Not described
8085 timing, the exact flag behaviour of DAA, and the 8085’s undocumented flags (V and K).