Operands: r a register B C D E H L A or (HL); rr a pair BC DE HL SP;
n an 8-bit and nn a 16-bit number; d a signed 8-bit displacement; cc a condition
NZ Z NC C PO PE P M. Bytes and T are for the first form listed; the others follow the
text. A DD or FD prefix on an instruction that uses HL, H, L or (HL)
adds 1 byte and 4 T-states, and for (IX+d) adds 1 byte (the displacement) and 12 T-states (9 for LD (IX+d),n). Flags are the
ones changed, including the undocumented Y and X where the result sets them (flags).
Where a count has two values it is “not taken / taken” or “last / repeating”. Counts are the manual’s, and were each compared with real cores.
Load, exchange and stack
| Mnemonic | Forms | Bytes | T | Flags | What it does |
|---|---|---|---|---|---|
LD | r,r' · r,n · r,(HL) · (HL),r · (HL),n · A,(BC) · A,(DE) · (BC),A · (DE),A · A,(nn) · (nn),A · rr,nn · HL,(nn) · (nn),HL · SP,HL · r,(IX+d) · (IX+d),r · (IX+d),n · ED: rr,(nn) · (nn),rr · I,A · R,A · A,I · A,R | 1–4 | 4 (r,r) · 7 (r,n; with (HL)) · 10 (rr,nn; (HL),n) · 13 (A,(nn)) · 16 (HL,(nn)) · 20 (rr,(nn) in ED) · 6 (SP,HL) · 19 ((IX+d)) · 9 (I,A; A,I) | none, except A,I and A,R: S Z Y H X P N (P is IFF2) | Copy the source into the destination. |
PUSH | BC DE HL AF IX IY | 1 (2 for IX, IY) | 11 (15 for IX, IY) | none | Push a pair on the stack: SP is decreased by 2. |
POP | BC DE HL AF IX IY | 1 (2) | 10 (14) | all, for POP AF | Pull a pair from the stack. |
EX | DE,HL · AF,AF' · (SP),HL · (SP),IX · (SP),IY | 1 (2) | 4 · 4 · 19 (23 for IX, IY) | all, for AF,AF' | Exchange two registers, or a register with the top of the stack. |
EXX | 1 | 4 | none | Exchange BC DE HL with the shadow set BC' DE' HL'. |
Arithmetic and logic
| Mnemonic | Forms | Bytes | T | Flags | What it does |
|---|---|---|---|---|---|
ADD | A,r · A,n · A,(IX+d) · HL,rr · IX,rr | 1–3 | 4 (r) · 7 (n; (HL)) · 11 (HL,rr) · 19 ((IX+d)) · 15 (IX,rr) | S Z Y H X P(V) N C; for 16-bit: Y H X N C | Add. |
ADC | A,r · A,n · HL,rr (ED) | 1–2 | 4 · 7 · 15 (HL,rr) | all | Add with the carry flag. |
SUB | r · n | 1–2 | 4 · 7 | all | Subtract from A. |
SBC | A,r · A,n · HL,rr (ED) | 1–2 | 4 · 7 · 15 | all | Subtract with the carry flag. |
AND | r · n | 1–2 | 4 · 7 | all (H set, N and C cleared) | Bitwise AND with A. |
XOR | r · n | 1–2 | 4 · 7 | all (H, N, C cleared) | Bitwise exclusive OR with A. |
OR | r · n | 1–2 | 4 · 7 | all (H, N, C cleared) | Bitwise OR with A. |
CP | r · n | 1–2 | 4 · 7 | all (X and Y from the operand) | Compare with A: a subtraction that keeps only the flags. |
INC | r · rr · (IX+d) | 1–3 | 4 (r) · 11 ((HL)) · 6 (rr) · 23 ((IX+d)) | S Z Y H X P(V) N for 8-bit; none for 16-bit | Add 1. |
DEC | r · rr · (IX+d) | 1–3 | 4 · 11 · 6 · 23 | S Z Y H X P(V) N for 8-bit; none for 16-bit | Subtract 1. |
DAA | 1 | 4 | S Z Y H X P C (reads N H C) | Adjust A to packed decimal after an addition or subtraction. | |
CPL | 1 | 4 | Y H X N | Complement A. | |
NEG | (ED 44) | 2 | 8 | all | Negate A. |
CCF | 1 | 4 | Y H X N C | Complement the carry flag. | |
SCF | 1 | 4 | Y H X N C | Set the carry flag. |
Rotate, shift and bit
| Mnemonic | Forms | Bytes | T | Flags | What it does |
|---|---|---|---|---|---|
RLCA | 1 | 4 | Y H X N C | Rotate A left; bit 7 goes to bit 0 and to carry. | |
RRCA | 1 | 4 | Y H X N C | Rotate A right; bit 0 goes to bit 7 and to carry. | |
RLA | 1 | 4 | Y H X N C | Rotate A left through carry. | |
RRA | 1 | 4 | Y H X N C | Rotate A right through carry. | |
RLC | r · (IX+d) (CB) | 2 (4) | 8 · 15 ((HL)) · 23 ((IX+d)) | all | Rotate left. |
RRC | as RLC | 2 (4) | 8 · 15 · 23 | all | Rotate right. |
RL | as RLC | 2 (4) | 8 · 15 · 23 | all | Rotate left through carry. |
RR | as RLC | 2 (4) | 8 · 15 · 23 | all | Rotate right through carry. |
SLA | as RLC | 2 (4) | 8 · 15 · 23 | all | Shift left; bit 0 becomes 0. |
SRA | as RLC | 2 (4) | 8 · 15 · 23 | all | Shift right keeping bit 7. |
SRL | as RLC | 2 (4) | 8 · 15 · 23 | all | Shift right; bit 7 becomes 0. |
BIT | b,r · b,(HL) · b,(IX+d) | 2 (4) | 8 · 12 ((HL)) · 20 ((IX+d)) | S Z Y H X P N (Z set when the bit is 0; H set; Y and X come from the operand, or from the address for memory) | Test bit b. |
RES | b,r · b,(HL) · b,(IX+d) | 2 (4) | 8 · 15 · 23 | none | Clear bit b. |
SET | as RES | 2 (4) | 8 · 15 · 23 | none | Set bit b. |
RLD | (ED 6F) | 2 | 18 | S Z Y H X P N | Rotate the three nibbles A(low) and (HL) left by one nibble. |
RRD | (ED 67) | 2 | 18 | S Z Y H X P N | The same, right. |
Jump, call and return
| Mnemonic | Forms | Bytes | T | Flags | What it does |
|---|---|---|---|---|---|
JP | nn · cc,nn · (HL) · (IX) · (IY) | 3 (1; 2) | 10 · 10 · 4 (8 for IX, IY) | none (reads the flag for cc) | Jump to the address; JP (HL) jumps to the address in HL (not to the byte it points at). |
JR | d · cc,d (NZ Z NC C only) | 2 | 12 · 7 / 12 | none | Jump relative to the next instruction. |
DJNZ | d | 2 | 8 / 13 | none | Decrement B, jump relative if it is not zero. |
CALL | nn · cc,nn | 3 | 17 · 10 / 17 | none | Push the return address, then jump. |
RET | · · cc | 1 | 10 · 5 / 11 | none | Pull the return address into PC. |
RETI | (ED 4D) | 2 | 14 | none | Return from a maskable interrupt (recognised by the Z80 peripheral chips). |
RETN | (ED 45) | 2 | 14 | none | Return from the non-maskable interrupt: IFF1 is restored from IFF2. |
RST | $00 $08 … $38 | 1 | 11 | none | Call the fixed address. |
Block, search and I/O
| Mnemonic | Forms | Bytes | T | Flags | What it does |
|---|---|---|---|---|---|
LDI | 2 | 16 | Y H X P N | Copy (HL) to (DE); increment HL and DE; decrement BC (P/V is BC≠0). | |
LDD | 2 | 16 | Y H X P N | As LDI, decrementing HL and DE. | |
LDIR | 2 | 16 / 21 | Y H X P N | Repeat LDI until BC is 0 (21 T-states per pass, 16 on the last). | |
LDDR | 2 | 16 / 21 | Y H X P N | Repeat LDD until BC is 0. | |
CPI | 2 | 16 | S Z Y H X P N | Compare A with (HL); increment HL; decrement BC. | |
CPD | 2 | 16 | S Z Y H X P N | As CPI, decrementing HL. | |
CPIR | 2 | 16 / 21 | S Z Y H X P N | Repeat CPI until BC is 0 or A equals (HL). | |
CPDR | 2 | 16 / 21 | S Z Y H X P N | Repeat CPD until BC is 0 or A equals (HL). | |
IN | A,(n) · r,(C) | 2 | 11 · 12 | none for A,(n); S Z Y H X P N for r,(C) | Read a port. (n) puts A on the upper address lines; (C) puts B there. |
OUT | (n),A · (C),r | 2 | 11 · 12 | none | Write a port. |
INI | 2 | 16 | S Z Y H X P N C (Z and N documented) | Read the port at BC into (HL); decrement B; increment HL. | |
IND | 2 | 16 | as INI | As INI, decrementing HL. | |
INIR | 2 | 16 / 21 | as INI | Repeat INI until B is 0. | |
INDR | 2 | 16 / 21 | as INI | Repeat IND until B is 0. | |
OUTI | 2 | 16 | as INI | Write (HL) to the port at BC; decrement B; increment HL. | |
OUTD | 2 | 16 | as INI | As OUTI, decrementing HL. | |
OTIR | 2 | 16 / 21 | as INI | Repeat OUTI until B is 0. | |
OTDR | 2 | 16 / 21 | as INI | Repeat OUTD until B is 0. |
CPU control
| Mnemonic | Forms | Bytes | T | Flags | What it does |
|---|---|---|---|---|---|
NOP | 1 | 4 | none | Do nothing. | |
HALT | 1 | 4 | none | Run NOPs until an interrupt. | |
DI | 1 | 4 | none | Clear IFF1 and IFF2. | |
EI | 1 | 4 | none | Set IFF1 and IFF2 after the next instruction. | |
IM | 0 · 1 · 2 (ED 46, 56, 5E) | 2 | 8 | none | Set the interrupt mode. |
Undocumented instructions
These are not in Zilog’s manual. Sean Young’s The Undocumented Z80 Documented describes them, and every one of them was run on at least one real emulator core (see the checks). The viewer marks them undocumented.
Prefixes that change nothing
A DD or FD followed by an opcode that uses none of H L HL (HL) is ignored by that opcode but takes 4 T-states
and a refresh cycle. A run of them is allowed. The viewer shows each as dd or fd, one byte long. The cores differ in how they
count it: two run the prefix and the next instruction as one step, one as two.
IXH, IXL, IYH, IYL
With a DD or FD prefix an opcode that uses H or L (and no (HL)) uses the upper or lower half of
IX or IY instead: LD A,IXH, LD IXL,n, ADD A,IXL, INC IXH, LD IXH,IXL and so on, 46 opcodes each for DD and FD. They cost 4 T-states more than the unprefixed form.
Where an opcode has an (IX+d) operand, H and L stay H and L (LD H,(IX+d)). One real core (the pacman core) writes L
instead of IXL for LD IXL,r: that is a fault of that core.
SLL (SL1, SLS)
CB 30–CB 37: shift left and set bit 0 to 1. It fills the slot between SRA and SRL in the rotate table. Timing and flags are those of SLA.
DDCB and FDCB register copies, and BIT duplicates
DD CB d op with op low bits not 6: the operation is done on (IX+d) and the result is also copied into the register named by bits 0–2:
RLC (IX+d),B, RES 0,(IX+d),C, SET 7,(IX+d),A. For BIT every opcode with a different register is a duplicate
of BIT b,(IX+d). SLL (IX+d) (op 36) is undocumented too. The nascom core behaves differently from the other two for these;
the eZ80 core of the Agon emulator applies the prefix to H and L in the copy.
Repeated ED opcodes
| ED opcodes | Same as |
|---|---|
4C 54 5C 64 6C 74 7C | NEG (ED 44) |
55 5D 65 6D 75 7D | RETN (ED 45); ED 4D is the documented RETI |
4E 66 6E | IM 0 (ED 4E is sometimes called IM 0/1) |
76 | IM 1 (ED 56) |
7E | IM 2 (ED 5E) |
63 | LD (nn),HL (22), one byte longer |
6B | LD HL,(nn) (2A), one byte longer |
IN F,(C)
ED 70: reads the port at BC, sets the flags from it and discards the byte.
OUT (C),0
ED 71: writes 0 to the port at BC on an NMOS Z80 (255 on a CMOS Z80).
ED NOPs
Every ED opcode not listed on the ED map (including ED 77 and ED 7F) does nothing for 8 T-states. The pacman core stops with an error on some of them.
Sources
- Z80 CPU User Manual (UM0080) – Zilog: instruction set, lengths and T-states
- The Undocumented Z80 Documented – Sean Young: the undocumented instructions and flags
Not described
Bit-exact rules for the X and Y flags of the block and I/O instructions and of BIT n,(HL) (the MEMPTR register), and
which Z80 revisions differ (NMOS and CMOS) beyond OUT (C),0.