Zicsr: control and status register instructions
Opcode 1110011 (SYSTEM), I-format: bits 31:20 are the CSR number, funct3 the operation. The explorer writes the
CSR by name when it has one (the CSR list) and in hex otherwise. The
immediate forms take a five-bit unsigned number in the rs1 field. A csrrs or csrrc
with rs1 = x0 (and the immediate forms with a zero immediate) does not write the CSR; csrrw with
rd = x0 does not read it.
| Instruction | funct3 | Operands | What it does |
|---|---|---|---|
csrrw | 001 | rd, csr, rs1 | rd = csr; csr = rs1. |
csrrs | 010 | rd, csr, rs1 | rd = csr; csr = csr or rs1. |
csrrc | 011 | rd, csr, rs1 | rd = csr; csr = csr and not rs1. |
csrrwi | 101 | rd, csr, uimm | As csrrw with an immediate. |
csrrsi | 110 | rd, csr, uimm | As csrrs with an immediate. |
csrrci | 111 | rd, csr, uimm | As csrrc with an immediate. |
Zifencei
| Instruction | Encoding | What it does |
|---|---|---|
fence.i | 0x0000100f (opcode 0001111, funct3 001) | Makes instruction fetches see the stores this hart did before it. |
Privileged instructions (SYSTEM, funct3 000)
| Instruction | Encoding | What it does |
|---|---|---|
ecall, ebreak | 0x00000073, 0x00100073 | See the base page. |
mret | 0x30200073 | Return from a machine-mode trap: pc = mepc. |
sret | 0x10200073 | Return from a supervisor-mode trap: pc = sepc. |
mnret | 0x70200073 | Return from a resumable non-maskable interrupt (Smrnmi). |
dret | 0x7b200073 | Return from debug mode (the debug specification). |
wfi | 0x10500073 | Waits for an interrupt; an implementation may treat it as a no-operation. |
sfence.vma | funct7 0001001, rd = 0; operands rs1 (address), rs2 (ASID) | Orders stores to page tables before address translation; the address and ASID narrow the effect (x0 means all). |
sinval.vma, sfence.w.inval, sfence.inval.ir | funct7 0001011 (rs1, rs2); 0x18000073; 0x18100073 | Svinval: the invalidation split from the ordering, so that many entries can be invalidated with one fence pair. |
wrs.nto, wrs.sto | 0x00d00073, 0x01d00073 | Zawrs: wait on the reservation set, with no or a short timeout. |
The decoder always reads these, whatever the profile: the privileged architecture is not one of the extensions an architecture string names. The hypervisor instructions are on the H page.
Zicbom, Zicboz, Zicbop: cache-block operations
| Instruction | Encoding | What it does |
|---|---|---|
cbo.inval, cbo.clean, cbo.flush (Zicbom) | MISC-MEM, funct3 010, rd = 0, bits 31:20 = 0, 1, 2; operand (rs1) | Invalidate; write back; write back and invalidate the cache block holding the address. |
cbo.zero (Zicboz) | as above, bits 31:20 = 4 | Zero the whole cache block. |
prefetch.i, prefetch.r, prefetch.w (Zicbop) | ORI with rd = 0 (a HINT encoding), rs2 field = 0, 1, 3; the immediate’s low five bits are zero | Prefetch the block for instruction fetch, reading or writing; operand offset(rs1) with the offset a multiple of 32. |
Zimop, Zihintpause, Zihintntl, Zicond
| Instruction | Encoding | What it does |
|---|---|---|
mop.r.0 to mop.r.31 | SYSTEM, funct3 100: 1 n4 00 n3:2 0111 n1:0 rs1 100 rd | May-be-operations: write 0 to rd unless a later extension gives the encoding a meaning. The compressed forms (Zcmop) are not decoded. |
mop.rr.0 to mop.rr.7 | SYSTEM, funct3 100: 1 n2 00 n1:0 1 rs2 rs1 100 rd | The two-source form. |
pause | 0x0100000f | A hint that the hart is in a spin-wait loop. |
ntl.p1, ntl.pall, ntl.s1, ntl.all (and c.ntl.*) | add x0, x0, x2 to x5 | Hints that the next memory access has non-temporal locality at the named cache level. |
czero.eqz, czero.nez | OP, funct7 0000111, funct3 101, 111 | rd = 0 if rs2 is zero (or non-zero), else rs1: a conditional move in two instructions. |