Introduction
A CSR is addressed by a 12-bit number. Bits 11:10 say whether it is read-only (11) or read/write; bits 9:8 give the
lowest privilege level that may access it (00 user, 01 supervisor, 10 hypervisor or virtual supervisor, 11 machine). The
numbers 0x7a0 to 0x7af are the trigger module (machine mode) and 0x7b0 to 0x7bf the debug CSRs (debug mode only). The
names below are what the explorer writes; the names a number gets in the decoder are the same as those of
llvm-mc for all 4096 numbers, apart from vendor-specific CSRs, which have no name here. Names ending
in h exist only on RV32 (the upper 32 bits of a 64-bit register); on RV64 the number has no name.
Odd-numbered pmpcfg registers exist only on RV32.
User level
| Number | Name | Extension | What it is |
|---|---|---|---|
| 0x001 | fflags | F | Floating-point accrued exceptions (NX, UF, OF, DZ, NV) |
| 0x002 | frm | F | Dynamic rounding mode |
| 0x003 | fcsr | F | frm and fflags together |
| 0x008, 0x009, 0x00a, 0x00f | vstart, vxsat, vxrm, vcsr | V | Vector start position, fixed-point saturation flag and rounding mode, and the last two together |
| 0x011 | ssp | Zicfiss | Shadow stack pointer |
| 0x015 | seed | Zkr | Entropy source |
| 0x017 | jvt | Zcmt | Jump vector table base |
| 0xc00, 0xc01, 0xc02 | cycle, time, instret | Zicntr | Read-only shadows of the machine counters |
| 0xc03 to 0xc1f | hpmcounter3 to hpmcounter31 | Zihpm | Performance-monitoring counters |
| 0xc80 to 0xc82, 0xc83 to 0xc9f | cycleh, timeh, instreth, hpmcounter3h to hpmcounter31h | RV32 | Upper halves |
| 0xc20, 0xc21, 0xc22 | vl, vtype, vlenb | V | Vector length, vector type, vector register length in bytes |
Supervisor level
| Number | Name | What it is |
|---|---|---|
| 0x100 | sstatus | Status (the supervisor view of mstatus) |
| 0x104 | sie | Interrupt enable |
| 0x105 | stvec | Trap vector base and mode |
| 0x106 | scounteren | Counter enable |
| 0x10a | senvcfg | Environment configuration |
| 0x10c to 0x10f | sstateen0 to sstateen3 | State enable (Smstateen) |
| 0x114 | sieh | Upper half of sie (RV32, Ssaia) |
| 0x120 | scountinhibit | Counter inhibit (Smcdeleg) |
| 0x140 to 0x144 | sscratch, sepc, scause, stval, sip | Scratch, exception pc, trap cause, bad address or instruction, interrupt pending |
| 0x14d, 0x15d | stimecmp, stimecmph | Timer compare (Sstc) |
| 0x14c to 0x14f, 0x15f | sctrctl, sctrstatus, sctrdepth | Control transfer records (Ssctr) |
| 0x150 to 0x157, 0x15c | siselect, sireg, sireg2 to sireg6, siph, stopei | Indirect CSR access and the advanced interrupt architecture (Ssaia, Sscsrind) |
| 0x180 | satp | Address translation and protection |
| 0x181 | srmcfg | Resource management configuration (Ssqosid) |
| 0x5a8 | scontext | Trigger context (Sdtrig) |
| 0xda0, 0xdb0 | scountovf, stopi | Counter overflow (Sscofpmf), top interrupt (Ssaia) |
Hypervisor and virtual supervisor
| Number | Name | What it is |
|---|---|---|
| 0x600, 0x602 to 0x607, 0x60a | hstatus, hedeleg, hideleg, hie, htimedelta, hcounteren, hgeie, henvcfg | Hypervisor status, delegation, enables and configuration |
| 0x608, 0x609 | hvien, hvictl | Virtual interrupt enables and control (Ssaia) |
| 0x60c to 0x60f | hstateen0 to hstateen3 | State enable (Smstateen) |
| 0x612, 0x613, 0x615, 0x618, 0x61a, 0x61c to 0x61f | hedelegh, hidelegh, htimedeltah, hvienh, henvcfgh, hstateen0h to hstateen3h | Upper halves (RV32) |
| 0x643 to 0x645, 0x64a | htval, hip, hvip, htinst | Bad guest physical address, interrupt pending, virtual interrupt pending, trapped instruction |
| 0x646, 0x647, 0x655 to 0x657 | hviprio1, hviprio2, hviph, hviprio1h, hviprio2h | VS-level interrupt priorities (Ssaia) |
| 0x680, 0x6a8, 0xe12 | hgatp, hcontext, hgeip | Guest address translation, trigger context, guest external interrupts pending |
| 0x200, 0x204, 0x205, 0x240 to 0x244, 0x280 | vsstatus, vsie, vstvec, vsscratch, vsepc, vscause, vstval, vsip, vsatp | The guest’s copies of the supervisor CSRs |
| 0x214, 0x24d, 0x24e, 0x250 to 0x257, 0x25c, 0x25d, 0xeb0 | vsieh, vstimecmp, vsctrctl, vsiselect, vsireg, vsireg2 to vsireg6, vsiph, vstopei, vstimecmph, vstopi | Guest timer, indirect access and interrupt CSRs |
Machine level
| Number | Name | What it is |
|---|---|---|
| 0xf11 to 0xf15 | mvendorid, marchid, mimpid, mhartid, mconfigptr | Vendor, architecture and implementation IDs, hart ID, configuration pointer |
| 0x300 to 0x306 | mstatus, misa, medeleg, mideleg, mie, mtvec, mcounteren | Status, ISA, delegation, interrupt enable, trap vector, counter enable |
| 0x308, 0x309, 0x30a, 0x310, 0x312 | mvien, mvip, menvcfg, mstatush, medelegh | Virtual interrupts, environment configuration, upper halves (RV32) |
| 0x30c to 0x30f, 0x31c to 0x31f | mstateen0 to mstateen3, …h | State enable (Smstateen) |
| 0x313, 0x314, 0x318, 0x319, 0x31a | midelegh, mieh, mvienh, mviph, menvcfgh | Upper halves (RV32) |
| 0x320 to 0x322 | mcountinhibit, mcyclecfg, minstretcfg | Counter inhibit and privilege-mode filtering |
| 0x323 to 0x33f | mhpmevent3 to mhpmevent31 | Event selectors |
| 0x340 to 0x344 | mscratch, mepc, mcause, mtval, mip | Scratch, exception pc, trap cause, bad address, interrupt pending |
| 0x34a, 0x34b | mtinst, mtval2 | Trapped instruction, guest physical address |
| 0x34e, 0x350 to 0x357, 0x35c, 0xfb0 | mctrctl, miselect, mireg, mireg2 to mireg6, miph, mtopei, mtopi | Control transfer records, indirect access and advanced interrupts |
| 0x3a0 to 0x3af, 0x3b0 to 0x3ef | pmpcfg0 to pmpcfg15, pmpaddr0 to pmpaddr63 | Physical memory protection |
| 0x740, 0x741, 0x742, 0x744 | mnscratch, mnepc, mncause, mnstatus | Resumable NMI (Smrnmi) |
| 0x747, 0x757 | mseccfg, mseccfgh | Security configuration (Smepmp) |
| 0x721, 0x722, 0x723 to 0x73f | mcyclecfgh, minstretcfgh, mhpmevent3h to mhpmevent31h | Upper halves (RV32) |
| 0xb00, 0xb02, 0xb03 to 0xb1f | mcycle, minstret, mhpmcounter3 to mhpmcounter31 | Machine counters |
| 0xb80, 0xb82, 0xb83 to 0xb9f | mcycleh, minstreth, mhpmcounter3h to mhpmcounter31h | Upper halves (RV32) |
Trigger and debug
| Number | Name | What it is |
|---|---|---|
| 0x7a0 to 0x7a5 | tselect, tdata1, tdata2, tdata3, tinfo, tcontrol | Trigger module (Sdtrig) |
| 0x7a8, 0x7aa | mcontext, mscontext | Trigger context |
| 0x7b0 to 0x7b3 | dcsr, dpc, dscratch0, dscratch1 | Debug mode (Sdext) |
Not described
CSRs in the custom ranges (0x5c0 to 0x5ff, 0x6c0 to 0x6ff, 0x7c0 to 0x7ff, 0x9c0 to 0x9ff, 0xdc0 to 0xdff, 0xfc0 to 0xfff and similar) belong to the implementer, and so do vendor extensions’ CSRs (SiFive, Andes, T-Head and others); the decoder shows them as hex numbers. The bits of each register are not described here.