RISC-V Instruction Set – Registers and ABI names

Introduction

There are 32 integer registers, x0 to x31, each as wide as the word size (XLEN: 32 or 64 bits). x0 always reads as zero and ignores writes. The program counter is a separate register with no number. With the floating-point extensions there are 32 more registers f0 to f31 (32, 64 or 128 bits wide: as wide as the widest of F, D and Q present), and with V there are 32 vector registers v0 to v31. The ABI names are those of the calling convention (the RISC-V ELF psABI); the explorer writes them unless the options bar asks for numbers.

Integer registers

The explorer writes s0, not fp. RV32E and RV64E have only x0 to x15; an instruction that names a higher register is reserved.

Floating-point registers

Vector registers

v0 to v31, no ABI names. v0 holds the mask for a masked instruction (written v0.t in the operands) and is the carry or select register of vadc and vmerge. A group of registers (LMUL 2, 4 or 8) is named by its first register.

Registers in compressed instructions

Most 16-bit instructions have room for only three bits of register number (the “primed” registers rd′, rs1′, rs2′), which name x8 to x15 (s0, s1, a0 to a5) or f8 to f15. Others have a five-bit register field, with a few using sp implicitly. The Zcmp instructions cm.mvsa01 and cm.mva01s name the s-registers by a three-bit number: 0 and 1 are s0 and s1, 2 to 7 are s2 to s7.

Control and status registers

A separate 4096-entry space of CSRs, read and written by the Zicsr instructions; see the CSR list.