Introduction
The 1802 is a register-transfer machine: the sixteen scratchpad registers hold addresses and counters, and the only arithmetic is on the accumulator D and a memory byte addressed by R(X). There is no stack pointer or program counter of fixed name: P and X choose which registers act as them.
The registers
| Register | Size | Role |
|---|---|---|
R0 to RF | 16 bits | The scratchpad. At reset P = 0 and X = 0, so R0 is the program counter and the program starts at address 0. In Studio II and Elf programs R2 is the usual stack, R3 and R4/R5 call and return registers. An interrupt makes R1 the program counter and R2 the data pointer (P = 1, X = 2). |
P | 4 bits | Which register is the program counter. SEP changes it; a SEP R5 starts executing at the address in R5: the subroutine call of the 1802. |
X | 4 bits | Which register is the data pointer R(X): the address of the memory byte of LDX, OR, AND, XOR, ADD, SD, SM and their carry forms, STXD, LDXA, OUT, INP, SAV, IRX, RET and DIS. SEX changes it. |
D | 8 bits | The accumulator. |
DF | 1 bit | The data flag: the carry of an addition, and for subtraction 1 when there was no borrow; the bit shifted out by a shift. Branches BDF and BNF test it. |
T | 8 bits | Holds X and P (X in the high nibble) during an interrupt and for MARK and SAV. |
Q | 1 bit | An output flip-flop (set by SEQ, cleared by REQ); on the Studio II it drives the beeper, on the Elf an LED. BQ and BNQ test it. |
IE | 1 bit | Interrupt enable: RET sets it, DIS clears it. LSIE skips when it is set. |
EF1 to EF4 | pins | Four external flag inputs, tested by B1 to B4 and BN1 to BN4 (a flag is "1" when its pin is low). |
Input and output
OUT and INP use the memory byte addressed by R(X). OUT n (opcodes 61 to 67) puts that byte on the data bus and the number n on the three N lines for
external hardware to decode, then increments R(X); INP n (69 to 6F) reads the bus into the memory byte at R(X) and into D. Port numbers are 1 to 7:
port 0 does not exist (opcode 60 is IRX, which only increments R(X), and 68 is reserved).
Where the one core read differs
The only 1802 core on the machine used for checking (the Cosmac Elf core of emulators.org) differs from the manual as remembered on two points; this decoder follows the manual: RET and DIS load X and P from the byte at R(X) and increment R(X): the core increments the register selected by the new X, the decoder reports the register that was R(X) before the load. A short branch whose operand byte is the last byte of a page (the opcode at xxFE) goes to the page of the operand byte; the core takes the following page. The manual itself could not be read for this work (the PDF’s text could not be extracted), so both rest on the Wikipedia and Emma 02 descriptions and memory of the manual.
Not described
Known, not yet covered
- Reference: the state machine (S0 fetch, S1 execute, S2 DMA, S3 interrupt), the CLEAR, WAIT and LOAD modes, and the machine-specific meaning of the ports and flags.
Unknown
- Reference: the exact order of the effects of RET when the loaded X or P equals the old R(X) register.