CDP1802 Instructions

Introduction

Each row gives the instruction, its opcode (a range is every register N or port), its length in bytes, its machine cycles (a machine cycle is eight clock pulses: most instructions take 2, the long branches, long skips and NOP take 3; the cycle count of IDL is not stated in the source read), what it does and whether it changes DF. RN is the register named by the low nibble, R(X) the register named by X, R(P) the program counter. Memory is only ever addressed through one of those.

Registers

Instruction	Opcode	Bytes	Cycles	What it does	DF
`INC`	`10-1F`	1	2	Increment RN.	no
`DEC`	`20-2F`	1	2	Decrement RN.	no
`GLO`	`80-8F`	1	2	D = the low byte of RN.	no
`GHI`	`90-9F`	1	2	D = the high byte of RN.	no
`PLO`	`A0-AF`	1	2	The low byte of RN = D.	no
`PHI`	`B0-BF`	1	2	The high byte of RN = D.	no
`SEP`	`D0-DF`	1	2	P = N: RN becomes the program counter (a call, or a return to the caller’s register). Execution continues at the address RN holds.	no
`SEX`	`E0-EF`	1	2	X = N: RN becomes the data pointer R(X).	no
`IRX`	`60`	1	2	Increment R(X).	no

Memory

Instruction	Opcode	Bytes	Cycles	What it does	DF
`LDN`	`01-0F`	1	2	D = the byte at the address in RN. (Opcode 00 is IDL: there is no LDN R0.)	no
`LDA`	`40-4F`	1	2	D = the byte at the address in RN, then RN = RN + 1.	no
`STR`	`50-5F`	1	2	Store D at the address in RN.	no
`LDX`	`F0`	1	2	D = the byte at R(X).	no
`LDXA`	`72`	1	2	D = the byte at R(X), then R(X) = R(X) + 1.	no
`STXD`	`73`	1	2	Store D at R(X), then R(X) = R(X) − 1 (a push).	no
`LDI`	`F8`	2	2	D = the immediate byte.	no

Logic and shifts

Instruction	Opcode	Bytes	Cycles	What it does	DF
`OR`	`F1`	1	2	D = D OR the byte at R(X).	no
`AND`	`F2`	1	2	D = D AND the byte at R(X).	no
`XOR`	`F3`	1	2	D = D XOR the byte at R(X).	no
`ORI`	`F9`	2	2	D = D OR the immediate byte.	no
`ANI`	`FA`	2	2	D = D AND the immediate byte.	no
`XRI`	`FB`	2	2	D = D XOR the immediate byte.	no
`SHR`	`F6`	1	2	Shift D right: bit 0 goes to DF, a zero comes into bit 7.	yes
`SHL`	`FE`	1	2	Shift D left: bit 7 goes to DF, a zero comes into bit 0.	yes
`SHRC`	`76`	1	2	Shift D right with carry: DF comes into bit 7, bit 0 goes to DF. Also called RSHR.	yes
`SHLC`	`7E`	1	2	Shift D left with carry: DF comes into bit 0, bit 7 goes to DF. Also called RSHL.	yes

Arithmetic

DF is the carry for additions and 1 when no borrow was needed for subtractions. SD subtracts D from memory; SM subtracts memory from D.

Instruction	Opcode	Bytes	Cycles	What it does	DF
`ADD`	`F4`	1	2	D = D + the byte at R(X).	yes
`ADC`	`74`	1	2	D = D + the byte at R(X) + DF.	yes
`ADI`	`FC`	2	2	D = D + the immediate byte.	yes
`ADCI`	`7C`	2	2	D = D + the immediate byte + DF.	yes
`SD`	`F5`	1	2	D = the byte at R(X) − D.	yes
`SDB`	`75`	1	2	D = the byte at R(X) − D − (1 − DF).	yes
`SDI`	`FD`	2	2	D = the immediate byte − D.	yes
`SDBI`	`7D`	2	2	D = the immediate byte − D − (1 − DF).	yes
`SM`	`F7`	1	2	D = D − the byte at R(X).	yes
`SMB`	`77`	1	2	D = D − the byte at R(X) − (1 − DF).	yes
`SMI`	`FF`	2	2	D = D − the immediate byte.	yes
`SMBI`	`7F`	2	2	D = D − the immediate byte − (1 − DF).	yes

Short branches

Two bytes: the target is on the page of the operand byte. BN1 to BN4 and B1 to B4 test the external flag pins.

Instruction	Opcode	Bytes	Cycles	What it does	DF
`BR`	`30`	2	2	Branch always.	no
`BQ`	`31`	2	2	Branch if Q = 1.	no
`BZ`	`32`	2	2	Branch if D = 0.	no
`BDF`	`33`	2	2	Branch if DF = 1. Also called BPZ and BGE.	no
`B1`	`34`	2	2	Branch if EF1 = 1.	no
`B2`	`35`	2	2	Branch if EF2 = 1.	no
`B3`	`36`	2	2	Branch if EF3 = 1.	no
`B4`	`37`	2	2	Branch if EF4 = 1.	no
`SKP`	`38`	2	2	Never branches: skips the next byte. Also called NBR.	no
`BNQ`	`39`	2	2	Branch if Q = 0.	no
`BNZ`	`3A`	2	2	Branch if D is not 0.	no
`BNF`	`3B`	2	2	Branch if DF = 0. Also called BM and BL.	no
`BN1`	`3C`	2	2	Branch if EF1 = 0.	no
`BN2`	`3D`	2	2	Branch if EF2 = 0.	no
`BN3`	`3E`	2	2	Branch if EF3 = 0.	no
`BN4`	`3F`	2	2	Branch if EF4 = 0.	no

Long branches and skips

All take 3 machine cycles. A long branch has a 16-bit target (high byte first); a long skip is one byte that skips the next two when its condition holds.

Instruction	Opcode	Bytes	Cycles	What it does	DF
`LBR`	`C0`	3	3	Long branch always.	no
`LBQ`	`C1`	3	3	Long branch if Q = 1.	no
`LBZ`	`C2`	3	3	Long branch if D = 0.	no
`LBDF`	`C3`	3	3	Long branch if DF = 1.	no
`NOP`	`C4`	1	3	No operation.	no
`LSNQ`	`C5`	1	3	Long skip if Q = 0.	no
`LSNZ`	`C6`	1	3	Long skip if D is not 0.	no
`LSNF`	`C7`	1	3	Long skip if DF = 0.	no
`LSKP`	`C8`	3	3	Always skips the next two bytes (shown with them). Also called NLBR.	no
`LBNQ`	`C9`	3	3	Long branch if Q = 0.	no
`LBNZ`	`CA`	3	3	Long branch if D is not 0.	no
`LBNF`	`CB`	3	3	Long branch if DF = 0.	no
`LSIE`	`CC`	1	3	Long skip if IE = 1.	no
`LSQ`	`CD`	1	3	Long skip if Q = 1.	no
`LSZ`	`CE`	1	3	Long skip if D = 0.	no
`LSDF`	`CF`	1	3	Long skip if DF = 1.	no

Control and input/output

Instruction	Opcode	Bytes	Cycles	What it does	DF
`IDL`	`00`	1	not stated	Idle: stop fetching until a DMA request, an interrupt or a reset.	no
`RET`	`70`	1	2	Return: (X, P) = the byte at R(X); R(X) = R(X) + 1; IE = 1.	no
`DIS`	`71`	1	2	Disable: as RET but IE = 0.	no
`SAV`	`78`	1	2	Store T at R(X).	no
`MARK`	`79`	1	2	T = (X, P); store T at R(2); X = P; R(2) = R(2) − 1.	no
`REQ`	`7A`	1	2	Reset Q (Q = 0).	no
`SEQ`	`7B`	1	2	Set Q (Q = 1).	no
`OUT`	`61-67`	1	2	Output the byte at R(X) with port N on the N lines, then R(X) = R(X) + 1.	no
`INP`	`69-6F`	1	2	Input from the bus (port N − 8) into the byte at R(X) and D.	no

CDP1802 Instruction Set – Instructions

Introduction

Registers

Memory

Logic and shifts

Arithmetic

Short branches

Long branches and skips

Control and input/output

Not described

Known, not yet covered

Unknown

Links

Reference