The register file
| Registers | Size | Use |
|---|---|---|
XWA XBC XDE XHL | 32, in four banks | General registers. Each has a 16-bit low half (WA BC DE HL) that splits into two bytes (W/A, B/C, D/E, H/L, the first of each pair the high byte), and a 16-bit high half (QWA QBC QDE QHL, bytes QW QA …). |
XIX XIY XIZ XSP | 32, one set | Index registers and the stack pointer, shared by all banks. Their halves are IX IY IZ SP and bytes IXL IXH … SPL SPH, with Q-prefixed upper halves. |
PC | 32 (24 used) | Program counter; the address space is 24 bits (16 MiB). |
SR | 16 | Status register (below); its low byte F holds the flags. |
F' | 8 | The alternate flag register: EX F,F' swaps it with F. |
XNSP XSSP | 32 | The user-mode (normal) and system-mode stack pointers; XSP is whichever the SYSM bit selects. |
Register banks
The bits RFP of SR (bits 10–8) choose the current bank of XWA XBC XDE XHL. An instruction writes the plain names (XWA, A) for the current bank,
the name with a prime (XWA', A') for the previous bank (RFP minus 1, modulo 4), and, in the Toshiba assembler,
RXWA3, RWA3, RA3 for a register of an absolute bank (here bank 3). The viewer uses these spellings; the option “Register bank names” writes XWA3 instead of RXWA3.
The spelling of the absolute-bank names is the assembler convention as remembered; the bank codes below are what the bytes say.
INCF and DECF add or subtract one from RFP (modulo 4), LDF #n loads it, POP SR and RETI restore it; an interrupt does not change it by itself.
The status register
| Bit | Name | Meaning |
|---|---|---|
| 15 | SYSM | System mode: 1 selects the system stack pointer |
| 14–12 | IFF | Interrupt mask level (0 to 7): an interrupt is taken only when its level is higher. EI n loads it; EI 7 is written DI. |
| 11 | MAX | Maximum/minimum mode flag (MAX, NORMAL) |
| 10–8 | RFP | Register file pointer: the current bank |
| 7 | S | Sign |
| 6 | Z | Zero |
| 5, 3 | – | Always 0 |
| 4 | H | Half carry (carry out of bit 3, used by DAA) |
| 2 | V | Overflow, or the parity of the result for the logical and shift instructions (P) |
| 1 | N | Subtract flag (set by subtraction, used by DAA) |
| 0 | C | Carry |
The value of SR after the Neo Geo Pocket starts a cartridge is $F800 in the RACE core (SYSM, interrupt level 7, MAX, bank 0).
The viewer lists, for each instruction, the flags it changes and the ones it reads (a condition code reads the flags it tests); a flag the manual leaves undefined after an instruction is marked
? in the instruction table and counted as changed.
Condition codes
| Code | cc | Alternative spelling | True when |
|---|---|---|---|
| 0 | F | never | |
| 1 | LT | S xor V | |
| 2 | LE | Z or (S xor V) | |
| 3 | ULE | C or Z | |
| 4 | OV | PE | V |
| 5 | MI | M | S |
| 6 | Z | EQ | Z |
| 7 | C | ULT | C |
| 8 | T | always (the viewer writes JR addr) | |
| 9 | GE | not (S xor V) | |
| A | GT | not (Z or (S xor V)) | |
| B | UGT | not (C or Z) | |
| C | NOV | PO | not V |
| D | PL | P | not S |
| E | NZ | NE | not Z |
| F | NC | UGE | not C |
The code is the low nibble of the opcode of JR ($60–$6F), JRL ($70–$7F) and of the second byte of JP, CALL, RET ($D0, $E0, $F0 rows of the destination table) and SCC ($70–$7F of the register tables).
Register codes
A register is named in an instruction either by a 3-bit number (the current bank’s W A B C D E H L for bytes; WA BC DE HL IX IY IZ SP or XWA … XSP for words and longs)
or by an 8-bit register code after a $C7, $D7 or $E7 prefix and inside the complex memory operands.
| Code | Register |
|---|---|
$00–$3F | Absolute bank n = code >> 4: $00 RXWA0, $04 RXBC0, $08 RXDE0, $0C RXHL0, then $10 … for bank 1, $20 bank 2, $30 bank 3 |
$40–$CF | No register (the viewer decodes the instruction with status reserved) |
$D0–$DF | The previous bank: $D0 XWA', $D4 XBC', $D8 XDE', $DC XHL' |
$E0–$EF | The current bank: $E0 XWA, $E4 XBC, $E8 XDE, $EC XHL |
$F0–$FF | $F0 XIX, $F4 XIY, $F8 XIZ, $FC XSP |
Inside each group of four codes the offset is the byte of the 32-bit register: a long register uses the code with the two low bits clear; a word register uses offset 0 (the low word, WA) or 2 (the high word, QWA); a byte register uses any offset,
$E0 A, $E1 W, $E2 QA, $E3 QW, $E4 C, $E5 B, and so on. A code that is not valid for the size of the instruction is shown with a question mark and the status reserved.
| 3-bit field | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
|---|---|---|---|---|---|---|---|---|
| Byte | W | A | B | C | D | E | H | L |
| Word | WA | BC | DE | HL | IX | IY | IZ | SP |
| Long | XWA | XBC | XDE | XHL | XIX | XIY | XIZ | XSP |
The same field is the register of a C8–CF, D8–DF, E8–EF prefix and the R of an ADD R,(mem)-style second byte (the byte table’s order W A B C … matches the byte layout of the registers: A is the low byte of WA).
Control registers
LDC cr,r and LDC r,cr move a register to or from a control register named by a code byte. The DMA names and codes below are the ones RACE’s source defines for its LDC registers (DMAS0 at $00 … DMAM3 at $2E), which agree with the Toshiba manual as remembered; INTNEST at $3C is from memory only, RACE does not name it. A code with no name here is shown as cr$xx with a note.
| Code | Register | Size |
|---|---|---|
$00 $04 $08 $0C | DMAS0 to DMAS3 | 32: DMA source address |
$10 $14 $18 $1C | DMAD0 to DMAD3 | 32: DMA destination address |
$20 $24 $28 $2C | DMAC0 to DMAC3 | 16: DMA transfer count |
$22 $26 $2A $2E | DMAM0 to DMAM3 | 8: DMA mode |
$3C | INTNEST | 16: interrupt nesting counter |
Not described
- The sizes of the control registers beyond RACE’s (DMAS and DMAD 32 bits, DMAC 16, DMAM 8; the manual’s table could not be read), and everything about
INTNEST. - What
MAXmode changes in the hardware beyond the SR bit. - The stack frames pushed by interrupts and
SWI(see the status page).